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[VHDL-FPGA-Verilog] gal DL : 0: 使用native图形引擎的数据结构和fb(Framebuffer)的驱动程序-Graphics engine using native data structures and fb (Framebuffer) driver
Date : 2025-12-29 Size : 10kb User : forrestyu
[VHDL-FPGA-Verilog] Moteur_test DL : 0: Engine for a test memory CY7C1062AV-Engine for a test memory CY7C1062AV33
Date : 2025-12-29 Size : 1kb User : guigui
[VHDL-FPGA-Verilog] tb_Moteur_test DL : 0: Test Bench for an engine code VHDL for CY7C1062AV-Test Bench for an engine code VHDL for CY7C1062AV33
Date : 2025-12-29 Size : 1kb User : guigui
[VHDL-FPGA-Verilog] 1DCT_VHDL DL : 0: VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.-VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.
Date : 2025-12-29 Size : 11kb User : NULL
[VHDL-FPGA-Verilog] vme_sv DL : 0: voice modulation engine, a DSP processor with test bench written in SystemVerilog
Date : 2025-12-29 Size : 8kb User : jijo
[VHDL-FPGA-Verilog] Oreilly.Programming.Google.App.Engine.Nov.2009.ra DL : 0: E-book: Oreilly.Programming.Google.App.Engine.Nov.2009
Date : 2025-12-29 Size : 3.01mb User : hank8617
[VHDL-FPGA-Verilog] can_latest[1].tar DL : 0: CAN，全称“Controller Area Network”，即控制器局域网，是国际上应用最广泛的现场总线之一。最初，CAN被设计作为汽车环境中的微控制器通讯，在车载各电子控制装置ECU之间交换信息，形成汽车电子控制网络。比如：发动机管理系统、变速箱控制器、仪表装备、电子主干系统中，均嵌入CAN控制装置。 -CAN, full name of the " Controller Area Network" , the Controller Area Network, is internationally the most widely used field bus. Initially, CAN is designed as a vehicle environment, the micro-controller communications, in-vehicle electronic control unit ECU of the exchange of information between the formation of automotive electronic control network. For example: engine management systems, transmission controllers, instrumentation and equipment, electronic backbone of the system are embedded CAN control.
Date : 2025-12-29 Size : 1.1mb User : zhaohaiting
[VHDL-FPGA-Verilog] top_interface DL : 0: top integrated block for 2d graphics engine
Date : 2025-12-29 Size : 1kb User : ashu
[VHDL-FPGA-Verilog] sms4_enc_engine DL : 0: SMS4算法加密引擎，Verilog语言-sms4 encryption engine, verilog
Date : 2025-12-29 Size : 2kb User : Scott
[VHDL-FPGA-Verilog] usb1_funct_latest.tar DL : 1: USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external micro-controller necessary. Derived from my USB 2.0 Function IP core, except all the high speed support logic has been ripped out and the interface was changed from shared memory to FIFO based. A basic test bench is now included as well. It should be viewed as a starting point to write a more comprehensive and complete test bench. I expect the users of this core to have some fundamental USB knowledge and be familiar with the UTMI specification and with the general USB transceivers (e.g. from philips). If you are not familiar with these two you should check out www.usb.org and read up on this subject ...
Date : 2025-12-29 Size : 58kb User : Andrey
[VHDL-FPGA-Verilog] JTAG-Engine DL : 0: A source code for JTAG access.
Date : 2025-12-29 Size : 7kb User : caicaizuo
[VHDL-FPGA-Verilog] LineEngine_tpf4 DL : 0: Designing a Line Engine for CPU in verilog
Date : 2025-12-29 Size : 6kb User : Mike R
[VHDL-FPGA-Verilog] UltraSensor-Vram-V8 DL : 0: Verilog语言编写的FPGA程序，有串口收发引擎代码，AD初始化采集代码,键盘扫描代码-FPGA Verilog language program, a serial port transceiver engine code, AD initialization acquisition code, the keyboard scan codes
Date : 2025-12-29 Size : 2.27mb User : guowuye
[VHDL-FPGA-Verilog] xapp859-rtl DL : 0: 在Xilinx V5或者V6下的dma引擎-In Xilinx V5 or V6 engine under the dma
Date : 2025-12-29 Size : 133kb User : tanghao
[VHDL-FPGA-Verilog] pidviaVhdl DL : 0: VHDL实现PID发动机转速控制,内置程序说明，一目了然-VHDL realize PID control engine speed, built-in program instructions at a glance
Date : 2025-12-29 Size : 3kb User : 焱斐然