Search - encryption and decryption algorithm

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[VHDL-FPGA-Verilog] SMS4_code DL : 0: 用Verilog实现国内第一个商用密码算法SMS4的加密和解密。-Using Verilog to achieve the first commercial cryptographic algorithm for encryption and decryption SMS4.
Date : 2025-12-30 Size : 204kb User : 闫伟伟
[VHDL-FPGA-Verilog] aes DL : 0: aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
Date : 2025-12-30 Size : 2.84mb User : cong
[VHDL-FPGA-Verilog] Verilog_study_book DL : 0: 现代计算机与通讯系统电子设备中广泛使用了数字信号处理专用集成电路，它们主要用于数字信号传输中所必需的滤波、变换、加密、解密、编码、解码、纠检错、压缩、解压缩等操作。这些处理工作从本质上说都是数学运算。从原则上讲，它们完全可以用计算机或微处理器来完成。这就是为什么我们常用C、Pascal 或汇编语言来编写程序，以研究算法的合理性和有效性的道理。-Modern computer and communication systems are widely used in electronic equipment for digital signal processing application specific integrated circuit, which is mainly used for digital signal transmission required for filtering, transformation, encryption, decryption, encoding, decoding, EDAC, compression, decompression, etc. operation. The processing in essence is math. In principle, they can use the computer or microprocessor to complete. That is why we used C, Pascal, or assembly language to write programs to study the rationality and effectiveness of the algorithm logic.
Date : 2025-12-30 Size : 1.94mb User : macray
[VHDL-FPGA-Verilog] rc4 DL : 0: RC4算法，WEP算法，加解密，密钥长度256-RC4 algorithm, WEP algorithm, encryption and decryption
Date : 2025-12-30 Size : 3kb User : shixu
[VHDL-FPGA-Verilog] Description-of-DES-with-VHDL DL : 0: 用VHDL描述DES算法用硬件的方式DES加解密体现了硬件编程人一般思想-DES algorithm using VHDL description of the way with hardware DES encryption and decryption hardware programming reflects the general thinking of people
Date : 2025-12-30 Size : 14kb User : lichen
[VHDL-FPGA-Verilog] SIMULATION-AND-SYNTHESIS-OF-TRIPLE-DES-BLOCK-CIPH DL : 0: This project presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these attacks. Triple DES was the answer to many of the shortcomings of DES. Since it is based on the DES algorithm, it is very easy to modify existing software to use Triple DES. It also has the advantage of proven reliability and a longer key length that eliminates many of the shortcut attacks that can be used to reduce the amount of time it takes to break DES. However, even this more powerful version of DES may not be strong enough to protect data for very much longer. The DES algorithm itself has become obsolete and is in need of replacement.DES encrypts data in 64-bit and it is a symmetric algorithm. The key length is 56-bits. KEY WORDS: DES, Encryption, Decryption, Cryptography, Simulation, Synthesis, TDES, Cipher.
Date : 2025-12-30 Size : 5.12mb User : abilash
[VHDL-FPGA-Verilog] AES_verilog DL : 1: 对AES算法加密解密的Verilog源代码，可以实现其128位和256位明文密文之间的转换。-AES algorithm for encryption and decryption of Verilog source code, can achieve the conversion of its 128 and 256 between the plaintext ciphertext.
Date : 2025-12-30 Size : 19kb User : 毛子明
[VHDL-FPGA-Verilog] AES DL : 0: AES算法加解密过程的Verilog代码，包括测试文件，通过FPGA验证。-AES algorithm encryption and decryption process Verilog code, including test files through the FPGA verification.
Date : 2025-12-30 Size : 16kb User : 郑雪松
[VHDL-FPGA-Verilog] AES DL : 0: AES加密和解密算法的硬件语言描述，很值得大家来学习！-AES hardware encryption and decryption algorithm description language, it is worth learning!
Date : 2025-12-30 Size : 12kb User : zhangwei
[VHDL-FPGA-Verilog] AES DL : 0: AES算法部分模块行位移列变换以及主题程序加密解密-AES algorithm transforms part of the module rows and columns relating to the displacement of encryption and decryption program
Date : 2025-12-30 Size : 455kb User : 秦川
[VHDL-FPGA-Verilog] Coding Files DL : 0: We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely accepted. All the cryptographic algorithms developed can be implemented with software or built with pure hardware. However with the help of Field Programmable Gate Arrays FPGA we tend to find expeditious solution and which can be easily upgraded to integrateany concordat changes. This contribution investigates the AES encryption and decryption cryptosystem with regard to FPGA and Very High Speed Integrated Circuit Hardware Description language VHDL. Optimized and Synthesizable VHDL code is developed for the implementation of both 128-bit data encryption and decryption process.
Date : 2025-12-30 Size : 27kb User : kutti