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[VHDL-FPGA-Verilog] DES DL : 0: DES　加密算法的实现，使用硬件描述语言VHDL编写-DES encryption algorithm realization, uses hardware description language VHDL to compile
Date : 2025-12-23 Size : 23kb User : zfhustb
[VHDL-FPGA-Verilog] fpga加密设计方法 DL : 0: FPGA加密的方法，对于那些需要加密自己的vhdl源代码的人来说，很有用-FPGA encryption methods for those who need to encrypt their VHDL source code in a way, very useful
Date : 2025-12-23 Size : 183kb User : 陶伟炯
[VHDL-FPGA-Verilog] des-verilog DL : 1: des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language
Date : 2025-12-23 Size : 66kb User : 杨云丰
[VHDL-FPGA-Verilog] ELEC_LOCK DL : 0: 4位电子密码锁，带键盘扫描、按键防抖动、LCD驱动编译码-four electronic password lock with a keyboard scan button shake, LCD driver encryption
Date : 2025-12-23 Size : 2kb User : xf
[VHDL-FPGA-Verilog] BBSdfbdgdr DL : 0: 如果遇到MD5加密文件，而又不知道密码的，请在数据库中换上这组加密的数据吧 16位：7a57a5a743894a0e 32位：21232f297a57a5a743894a0e4a801fc3 那么密码就是admin-if they MD5 encryption, and do not know the password. please database with a group of encrypted data it 16 : 7a57a5a743894a0e 32 : 21232f297a57a5a743894a0e4a801fc3 password is then ad min
Date : 2025-12-23 Size : 3.8mb User : 西西公主
[VHDL-FPGA-Verilog] ref-ualaw DL : 0: A率/u率压缩与解压缩的IP核，。 # 由AHDL语言写成，可在MaxplusII和QuartusII中使用，源代码加密。-A rate/u rate compression and decompression of the IP core,. By AHDL# languages, and the Quartus II MaxplusII use, the source code encryption.
Date : 2025-12-23 Size : 117kb User : zhangkun
[VHDL-FPGA-Verilog] hanmin DL : 0: 4位汉明编译码源代码。VHDL格式，经过仿真和测试通过，请放心使用。-four Hamming encryption source code. VHDL format, through simulation and test pass, please rest assured that use.
Date : 2025-12-23 Size : 135kb User : 田军卓
[VHDL-FPGA-Verilog] BasicRSA DL : 0: RSA加密算法的VHDL实现，通过实际FPGA验证。-RSA encryption algorithm of VHDL realize, through actual FPGA verification.
Date : 2025-12-23 Size : 9kb User : 张开文
[VHDL-FPGA-Verilog] AES_RTL DL : 0: 使用Verilog HDL 實現AES硬體加解密-Realize the use of Verilog HDL hardware AES encryption and decryption
Date : 2025-12-23 Size : 15kb User : 林夢魔
[VHDL-FPGA-Verilog] rc5_enc DL : 0: rc5的encryption,带state machine，一共四种状态st_idle,st_ready,st_round_op,st_pre_round-RC5 of encryption, with state machine, a total of four state st_idle, st_ready, st_round_op, st_pre_round
Date : 2025-12-23 Size : 2kb User : laSiA
[VHDL-FPGA-Verilog] aes DL : 0: vhdl implementation of the AES encryption algorithm
Date : 2025-12-23 Size : 239kb User : hesham
[VHDL-FPGA-Verilog] aesencryption DL : 0: Aes encryption on Fpga
Date : 2025-12-23 Size : 4kb User : Ibrahim
[VHDL-FPGA-Verilog] DES DL : 0: This is verilog source code for DES(Data Encryption standard) which is used in network security.
Date : 2025-12-23 Size : 20kb User : Krupesh
[VHDL-FPGA-Verilog] DES-HDL DL : 0: 用HDL实现的DES加密算法，通过前仿真，希望对大家有帮助-HDL implementation of the DES with the encryption algorithm, by pre-simulation, we want to help
Date : 2025-12-23 Size : 27kb User : su
[VHDL-FPGA-Verilog] DES DL : 0: 在ISE平台上，利用Verilog编程实现数据的DES加密-In the ISE platform, using Verilog programming DES data encryption
Date : 2025-12-23 Size : 646kb User : ldh
[VHDL-FPGA-Verilog] aes DL : 0: aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
Date : 2025-12-23 Size : 2.84mb User : cong
[VHDL-FPGA-Verilog] aes_pipe_latest.tar DL : 0: implementation of AES encryption algorithm in vhdl/verilog
Date : 2025-12-23 Size : 184kb User : cooldude
[VHDL-FPGA-Verilog] SEA DL : 0: Scalable Encryption Algorithm
Date : 2025-12-23 Size : 100kb User : Tri
[VHDL-FPGA-Verilog] sea DL : 0: Scalable Encryption Algorithm
Date : 2025-12-23 Size : 3kb User : Vinay
[VHDL-FPGA-Verilog] Coding Files DL : 0: We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely accepted. All the cryptographic algorithms developed can be implemented with software or built with pure hardware. However with the help of Field Programmable Gate Arrays FPGA we tend to find expeditious solution and which can be easily upgraded to integrateany concordat changes. This contribution investigates the AES encryption and decryption cryptosystem with regard to FPGA and Very High Speed Integrated Circuit Hardware Description language VHDL. Optimized and Synthesizable VHDL code is developed for the implementation of both 128-bit data encryption and decryption process.
Date : 2025-12-23 Size : 27kb User : kutti

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