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[VHDL-FPGA-Verilog] simple h264 vhdl encoder DL : 0: simple h264 encoder，source code and test code in vhdl，简单h264 硬件编码器，源代码及测试，vhdl语言
Date : 2011-01-06 Size : 389.92kb User : lida1204@gmail.com
[VHDL-FPGA-Verilog] tx_inter DL : 0: Convolutional Interleaver Encoder-convolutional Interleaver Encoder
Date : 2026-01-01 Size : 1kb User : 孙晓伟
[VHDL-FPGA-Verilog] RS(32to28)encoderanddecoder DL : 1: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Date : 2026-01-01 Size : 75kb User : 王文
[VHDL-FPGA-Verilog] bch_encoder_decoder DL : 0: bch encoder+decoder 源代码，Flash控制器，通讯都需要用到哦-bch encoder+ decoder source code, Flash controller, communications are needed Oh
Date : 2026-01-01 Size : 133kb User : linchan
[VHDL-FPGA-Verilog] encode DL : 0: Quartus下的RS（5，3）编码器的源程序，用Verilog语言编写。-Quartus under the RS (5,3) encoder source code, using Verilog language.
Date : 2026-01-01 Size : 3kb User : 桃子
[VHDL-FPGA-Verilog] 16b20b DL : 0: 以太网16B/20B源代码包括编码器和解码器功能-Ethernet 16B/20B source code including the encoder and decoder functions
Date : 2026-01-01 Size : 727kb User : asd
[VHDL-FPGA-Verilog] encoder DL : 0: VHDL实现循环码编码，设计了三个单元。switch是一个开关，shifter是移位寄存器，encoder是主体。-VHDL realization of cyclic code encoding, designed three modules. switch is a switch, shifter is the shift register, encoder is the main.
Date : 2026-01-01 Size : 2kb User : 王三一
[VHDL-FPGA-Verilog] 8b_10b DL : 0: vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later -VHDL prepared, 8b-10b codec design Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
Date : 2026-01-01 Size : 71kb User : 聂样
[VHDL-FPGA-Verilog] hamming.tar DL : 0: Verilog语言实现的Hamming(3,7)编码器，可用于FPGA实现-Verilog Language realize the Hamming (3,7) encoder, can be used to realize FPGA
Date : 2026-01-01 Size : 6kb User : 陈楚龙
[VHDL-FPGA-Verilog] mancheester_v DL : 1: 用Verilog HDL实现的曼彻斯特编码器和解码器。-Using Verilog HDL realize the Manchester encoder and decoder.
Date : 2026-01-01 Size : 9kb User : wangyunshann
[VHDL-FPGA-Verilog] crc_verilog DL : 0: 循环码编码器verilog实现，里面包含有源程序和仿真图。-Cyclic code encoder Verilog realization, which contains the source code and simulation of Fig.
Date : 2026-01-01 Size : 15kb User : 萍果
[VHDL-FPGA-Verilog] crc_16 DL : 0: 利用verilog实现的一个（2,1,2）卷积码的编码器,很有用的哟!-Verilog realize the use of a (2,1,2) convolutional code encoder, yo useful!
Date : 2026-01-01 Size : 1kb User : 刘横
[VHDL-FPGA-Verilog] RS_5_3_CODEC DL : 0: 用于数据块容错编码校验的芯片的RS编码器设计-Data blocks for fault-tolerant encoding check the RS encoder chip design
Date : 2026-01-01 Size : 3kb User : 李利歌
[VHDL-FPGA-Verilog] viterbi DL : 0: 卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
Date : 2026-01-01 Size : 250kb User : mediative
[VHDL-FPGA-Verilog] s3esk_rotary_encoder_interface DL : 0: 旋转编码器的decoder，具有消颤音功能-Rotary encoder decoder, with a vibrato function elimination
Date : 2026-01-01 Size : 274kb User : 于水
[VHDL-FPGA-Verilog] vhdl DL : 0: 最高优先级编码器和直流电机控制器,供初学者学习使用，方便快捷，有很强的参考价值-The highest priority encoder and DC motor controller, for beginners learning to use, convenient and has a strong reference value
Date : 2026-01-01 Size : 3kb User : 张楚荀
[VHDL-FPGA-Verilog] 8ENCODE DL : 0: 8位优先编码器 verilog CPLD EPM1270 源代码-8-bit priority encoder verilog CPLDEPM1270 source code
Date : 2026-01-01 Size : 110kb User : 韩思贤
[VHDL-FPGA-Verilog] CRC16bits DL : 0: 16bit crc encoder ande demo
Date : 2026-01-01 Size : 164kb User : chen
[VHDL-FPGA-Verilog] s3esk_rotary_encoder_interface DL : 0: Xilix spartan 3E 旋转编码器接口,脉冲方向识别,AB脉冲滤波 Rotary Encoder Interface Demonstrates how to use the rotary encoder portion of the rotary pushbutton switch.-Xilix spartan 3E rotary encoder interface, pulse direction identification, AB pulse filter Rotary Encoder InterfaceDemonstrates how to use the rotary encoder portion of the rotary pushbutton switch.
Date : 2026-01-01 Size : 273kb User : weihua yuan
[VHDL-FPGA-Verilog] Program of 4 to 2 Encoder DL : 0: Verilog code for encoder
Date : 2026-01-01 Size : 9kb User : maz1

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