Search - electronic bell

Search - electronic bell - List

[VHDL-FPGA-Verilog] 多功能电子钟 DL : 0: 具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.
Date : 2026-01-08 Size : 6kb User : 张建
[VHDL-FPGA-Verilog] 各段程序 DL : 0: 具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。 -with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.
Date : 2026-01-08 Size : 10kb User : 单明
[VHDL-FPGA-Verilog] electric_bell DL : 0: 电子打铃器在max plus 2 下编译通过-electronic bell playing for the max plus 2 under through compiler
Date : 2026-01-08 Size : 13kb User : wenquan
[VHDL-FPGA-Verilog] 111 DL : 0: 基于VHDL的电子钟，具有清零和重置功能，在一个程序中实现所有功能-VHDL-based electronic bell, with cleared and reset, in a process of realization of all functions
Date : 2026-01-08 Size : 1kb User : 李遥
[VHDL-FPGA-Verilog] clock DL : 0: vhdl写的电子钟例程，包括多个文件，者的参考。内容简练。作为教学用的。-write VHDL electronic bell routines, including more than documents, the reference. Concise content. Used as the medium of instruction.
Date : 2026-01-08 Size : 4kb User : cathy
[VHDL-FPGA-Verilog] 030501708 DL : 0: 用ＶＨＤＬ来模拟实现钟最终实现数字电子钟的设计，其中要用７段数码管-Use VHDL to simulate the final bell realize realize the design of digital electronic clock, which use 7 digital tube
Date : 2026-01-08 Size : 1.11mb User : chenli
[VHDL-FPGA-Verilog] UP3_CLOCK DL : 0: 采用vhdl语言编写的UP3开发板电子钟程序。在quartus中编译完成。-Using VHDL language UP3 development board electronic bell procedures. Compiled in the Quartus completed.
Date : 2026-01-08 Size : 68kb User : 小毛头
[VHDL-FPGA-Verilog] clock DL : 0: 用vhdl设计实现的多功能电子钟，可有日历，闹钟，修改等多种功能-With VHDL Design and Implementation of the multi-functional electronic bell, can have a calendar, alarm clock, to amend a variety of functions such as
Date : 2026-01-08 Size : 1.45mb User : fana
[VHDL-FPGA-Verilog] 5 DL : 0: 用VHDL语言实现电子钟-Using VHDL language electronic bell
Date : 2026-01-08 Size : 356kb User : chenyanli
[VHDL-FPGA-Verilog] clock DL : 0: 原创：基于VHDL语言编写的电子钟。采用模块化编写，可以调整时间，采用动态扫描显示时分秒-Original: Based on the VHDL language electronic bell. Modular prepared, you can adjust the time, dynamic scanning is displayed every minute
Date : 2026-01-08 Size : 514kb User : zzwuyu
[VHDL-FPGA-Verilog] eleclock DL : 0: VHDL实现的电子钟的基本功能，带QUARTUE工程文件-VHDL realization of the basic functions of electronic bell with engineering documents QUARTUE
Date : 2026-01-08 Size : 433kb User : fengyongsheng
[VHDL-FPGA-Verilog] clock DL : 0: 基于verilog HDL语言的电子钟，多功能电子时钟-Verilog HDL language-based electronic bell, electronic multi-function clock
Date : 2026-01-08 Size : 181kb User : 哈哈
[VHDL-FPGA-Verilog] Shuma DL : 0: 完整的电子钟程序，包含报时、定时、闹表的功能，其中包含了二十四进制，60进制计数器的设计，和顶层文件-Complete procedures for the electronic bell, including the time, from time to time, to make the function table, which contains 24 hexadecimal, 60 hexadecimal counter design, and top-level document
Date : 2026-01-08 Size : 887kb User : 李坤鹏
[VHDL-FPGA-Verilog] jow_order DL : 0: 这是我准备电子设计大赛时，用VHDL写的一个自动打铃系统，很好的学习资料。-This is when I am going to Electronic Design Contest, use VHDL to write an automatic bell playing system, a very good learning materials.
Date : 2026-01-08 Size : 3.24mb User : shuwei
[VHDL-FPGA-Verilog] mmpp33 DL : 0: 本电子钟由AT89C52单片机、555电路、报警电路，流水灯，校正时间电路、显示电路组成。-The electronic bell AT89C52 microcontroller, 555 circuits, alarm circuits, water lamp, the time correction circuit, display circuit.
Date : 2026-01-08 Size : 194kb User : 张园
[VHDL-FPGA-Verilog] clock_for_6.0 DL : 0: 基于FPGA的电子钟，开发环境是Quartus II 6.0。功能是3个按键分别设置时分秒。通常作为课程设计，供同学参考~-Electronic bell, development environment based on FPGA Quartus II 6.0. The function is the three buttons to set the hour, minute and second. Usually as courses designed for students to reference to
Date : 2026-01-08 Size : 540kb User : 小白
[VHDL-FPGA-Verilog] rs232 DL : 0: 串口传输，传输协议为RS232。RS-232C标准是美国EIA（电子工业联合会）与BELL等公司一起开发的1969年公布的通信协议。-Serial transmission, the transmission protocol for RS232. RS-232C standard communication protocol is developed with the EIA (Electronic Industries Association) BELL companies in the United States, published in 1969.
Date : 2026-01-08 Size : 3kb User : 陈恺
[VHDL-FPGA-Verilog] time DL : 0: FPGA做的电子钟，通过定时器实现。用vhdl做的led ip核，软件实现控制显示-FPGA do electronic bell, by timer implementation. Led ip vhdl do with nuclear, software control display
Date : 2026-01-08 Size : 14.08mb User : 勇磊