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[VHDL-FPGA-Verilog] zuosr8 DL : 0: Picasa 是Google提供的一个 Windows 应用程序；用户可以借助于该程序，在数秒钟内找到自己计算机上的图片，加以编辑并进行欣赏。-Picasa is the Google of a Windows application; Users can aid the process, in just a few seconds to find their own pictures on the computer, edit them and appreciate.
Date : 2025-12-24 Size : 3kb User : 孙潇
[VHDL-FPGA-Verilog] gal DL : 0: 用于编可编辑芯片用,如gal16v18芯片等,有几个文件, 内有说明等!-Series can be used to edit the chips used, such as chips gal16v18, there are several documents, there are descriptions!
Date : 2025-12-24 Size : 35kb User : mabaohua
[VHDL-FPGA-Verilog] jkchu DL : 0: jk触发器，自己尝试编辑的，用状态机实现，可以-jk flip-flop, try to edit their own, using state machine to achieve, you can
Date : 2025-12-24 Size : 80kb User : 谢小川
[VHDL-FPGA-Verilog] fenpin DL : 0: 分频器，自己尝试编辑的，20和40分频，可以-Divider, try to edit their own, 20 and 40 sub-band can be
Date : 2025-12-24 Size : 91kb User : 谢小川
[VHDL-FPGA-Verilog] Ultraedit_verilog DL : 0: 这个文件中提供了 verilog hdl 的在ultra edit32中编程所需要的语法-This document provides a verilog hdl in ultra edit32 programming required in grammar
Date : 2025-12-24 Size : 30kb User : 陈轩辕
[VHDL-FPGA-Verilog] bargraph3layer DL : 0: l-edit layout file of a bargraph
Date : 2025-12-24 Size : 218kb User : ss
[VHDL-FPGA-Verilog] abc DL : 0: cpld 的频率计的编程，利用程序编辑一个可变频率频率计-cpld programming frequency meter, use the procedure to edit a variable frequency frequency meter
Date : 2025-12-24 Size : 5.32mb User : gjygjy
[VHDL-FPGA-Verilog] drom DL : 0: FPGA rom硬件语言文件用于输出正弦序列数字信号--- megafunction wizard: ROM: 1-PORT -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: drom.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ --************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 8.0 Build 215 05/29/2008 SJ Full Version --************************************************************ --Copyright (C) 1991-2008 Altera Corporation --Your use of Altera Corporation s design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditi
Date : 2025-12-24 Size : 2kb User : 李小狼
[VHDL-FPGA-Verilog] Support-TP-CCIN-2012-2013 DL : 0: VHDL编辑PGCD的文件。实际上，这是上课时候老师给的。求通过验证-VHDL edit file of PGCD. In fact, this is the teacher gave during the class. Requirements through validation.
Date : 2025-12-24 Size : 4kb User : 李猜猜
[VHDL-FPGA-Verilog] jianyijiafaqi DL : 0: 采用MAX+PlusII工具编辑设计的Verilog程序设计的简易加法器。可实现10以内的加法计算-Using MAX+PlusII tools to edit the design of Verilog design of a simple adder. Can be realized within 10 addition calculation
Date : 2025-12-24 Size : 1.04mb User : 阿凡提
[VHDL-FPGA-Verilog] bw_scoresource DL : 0: This the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.-This is the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.
Date : 2025-12-24 Size : 6.36mb User : Yougnjae JIN
[VHDL-FPGA-Verilog] pci1 DL : 0: 如果想为了以后的2k平台兼容就最好编wdm，因为windows2k不支持vxd，而且以后的发展wdm肯定要代替vxd了。不过由于我找到的资料基本上都是介绍vxd的，感觉vxd的技术好像更成熟一点，编的人更多一点，所以偷了一下懒（惭愧），就没有去研究wdm，就选择了vxd。-If you want to later edit 2k on the best platform compatible wdm, because windows2k not support vxd, wdm and future development will certainly be replaced vxd it. However, because of the information I found basically introduced vxd, I feel a little more like vxd technologies mature, who compiled a little more, so stealing a bit lazy (shame), they did not go to study wdm, chose vxd.
Date : 2025-12-24 Size : 1kb User : luo
[VHDL-FPGA-Verilog] UpDownCounter DL : 0: This is an Up Down Counter coded in Verilog HDL. You can edit the bus width of this.
Date : 2025-12-24 Size : 6.12mb User : Patrick Go
[VHDL-FPGA-Verilog] Norflash DL : 0: 用verilog hdl写的Norflash控制器，可实现单字节读写，扇区擦除。-Norflash controller edit by Verilog hdl,it can read or write by Byte,or erase the sector.
Date : 2025-12-24 Size : 210kb User : 黄光奇
[VHDL-FPGA-Verilog] sp6ex1 DL : 0: 时钟二分频实例，详细介绍ISE中如何新建工程、创建并编辑源代码文件、进行语法检查、调用ModelSim进行功能仿真。-Clock two examples, detailed introduction of how to create a new project in ISE, create and edit the source code files, syntax checking, call ModelSim function simulation
Date : 2025-12-24 Size : 1004kb User : chi
[VHDL-FPGA-Verilog] pic10 DL : 0: 本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码，当然有一些模块是在quartus中直接编辑波形测试的，所以没有响应的测试脚本文件。 tri_state_port的测试还未完成，test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务其中有三篇文档： PIC10_RISC_Design.pdf:原文（verilog代码基本都来自原文，对一部分进行了改进），这篇文章写得非常好 PIC10F200_单片机IP核的实现.pdf:对上面的文章结合自己的实验过程进行了翻译和改写，给大家参考 PIC10F:PIC10系列单片机的手册-This folder inside the pic10 CPU is to achieve all the verilog code and the corresponding test script code, of course, there are some modules in quartus directly edit the waveform test, so there is no response to the test script file. Tri_state_port test has not yet completed, test_pic10_status_reg.vt and test_pic10_tri_state_port2.vt are not complete test tasks There are three documents: PIC10_RISC_Design.pdf: the original (verilog code basically the original, on a part of the improvement), this article is written very well PIC10F200_ IP core of the realization of single-chip.pdf: The above article combined with their own experimental process of translation and rewriting, for your reference PIC10F: PIC10 family of microcontrollers
Date : 2025-12-24 Size : 3.3mb User : Eddie