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[VHDL-FPGA-Verilog] traffic_1112 DL : 0: 一个交通灯的vhdl语言实现用ＶＣ的　　１．在指定的文件夹内查找某个文件　　　　　２．获取系统文件夹的路径，要求显示windows system temp 当前目录的路径Ｃ语言　　跳马问题：在５＊５的棋盘上，以编号为１的点出发，按日只跳马，要求不重复地跳所有位置，求出符合规则所有跳马的方案　　　　１　　６　　１５　　１０　　２１　　　　１４　９　　２０　　５　　　１６　　　　１９　２　　７　　　２２　　１１　　　　８　　１３　２４　　１７　　４　　　　２５　１８　３　　　１２　　２３ -a traffic light VHDL language of a VC. The designated folders to search within a document 2. Access to the system folder path, requested that the current windows system temp directory path C language vault : 5* 5 in the chessboard to the No. 1 starting point, the only daily vault and asked not to repeat all locations to jump to get in line with all rules of the program vault 1 6 15 10 21 14 9 20 5 16 19 2 7 22 11 8 13 24 17 4 25 18 3 12 23
Date : 2025-12-30 Size : 1kb User : 小三
[VHDL-FPGA-Verilog] dfgg DL : 0: 请先删除编译后的debug/release目录以减少压缩包大小-compiled the debug/release directory to reduce the size of compressed
Date : 2025-12-30 Size : 492kb User : lsm
[VHDL-FPGA-Verilog] user_logic_VGA_Controller DL : 0: user_logic_VGA_Controller，适合于DE2开发板，把这个文件夹放在工程目录之中，就可以在SOPC里直接添加VGA_Controller IP核了，很方便使用。-user_logic_VGA_Controller. suitable for Dictyophora development board, this folder on the project directory, it can be added directly SOPC Lane VGA_Controller IP core, very convenient to use.
Date : 2025-12-30 Size : 69kb User : 曾
[VHDL-FPGA-Verilog] LCD1602 DL : 0: LCD1602显示源代码 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是标准的16×2字符型液晶模块上显示字符串； 3-LCD1602 display the source code 1. Source file stored in the src directory, QII the project file stored in the directory Proj 2. Realize the function of the procedure is a standard 16 × 2 character LCD module to display the string 3
Date : 2025-12-30 Size : 700kb User : 张海风
[VHDL-FPGA-Verilog] 100vhdl DL : 0: VHDL源代码100例（1）自带目录！请仔细查看！-VHDL source code 100 cases (1) bring their own directory! Please review!
Date : 2025-12-30 Size : 95kb User : 李
[VHDL-FPGA-Verilog] 100vhdl1 DL : 0: VHDL源代码100例（1）带有目录！请仔细查看！-VHDL source code 100 cases (1) with the directory! Please review!
Date : 2025-12-30 Size : 23kb User : 李
[VHDL-FPGA-Verilog] 100vhdl2 DL : 0: VHDL源代码100例（1）带有目录！请仔细查看！-VHDL source code 100 cases (1) with the directory! Please review!
Date : 2025-12-30 Size : 54kb User : 李
[VHDL-FPGA-Verilog] 100vhdl3 DL : 0: VHDL源代码100例（1）带有目录！请仔细查看！-VHDL source code 100 cases (1) with the directory! Please review!
Date : 2025-12-30 Size : 27kb User : 李
[VHDL-FPGA-Verilog] 100vhdl4 DL : 0: VHDL源代码100例（1）带有目录！请仔细查看！-VHDL source code 100 cases (1) with the directory! Please review!
Date : 2025-12-30 Size : 4kb User : 李
[VHDL-FPGA-Verilog] ISP DL : 0: ISP的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-ISP of the IP core, can be used to download, unzip to the specified directory can be a light inside the read me.
Date : 2025-12-30 Size : 4kb User : 王鹏
[VHDL-FPGA-Verilog] altera_up_avalon_ps2 DL : 0: 花了半个月才改好的Atera DE1/DE2 ps2 IP 驱动核。放在FPGA工程目录下可以直接使用。本IP能够驱动PS/2键盘和鼠标。使用时只要调用HAL目录下的文件即可以直接使用！-Spent a good two weeks we have made some changes Atera DE1/DE2 ps2 IP-driven nuclear. On the FPGA project directory can be used directly. The IP to drive PS/2 keyboard and mouse. When used as long as the call HAL directory file that can be used directly!
Date : 2025-12-30 Size : 27kb User : 王乔
[VHDL-FPGA-Verilog] wordfile DL : 0: 这个文件中是UltraEdit的一些格式化文件说明由于原来的 UltraEdit 不支持 HDL 语言的格式化显示，把文件解压得到的 wordfile.txt替换其安装目录下的 wordfile.txt 文件即可-This document is formatted UltraEdit document describes some of the original UltraEdit as a result of HDL does not support formatting language shows that the document received decompression wordfile.txt replace its installation directory under the document can wordfile.txt
Date : 2025-12-30 Size : 31kb User : 钟毓秀
[VHDL-FPGA-Verilog] 4x4KEY DL : 0: 首先将下载板插到主板上面. 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能测试4×4键盘按键；具体的键值通过板上的数码管来显示。按下K1就显示1,K2就显示2.用户可以试试. 3。具体设计参考代码。-First, download the board into the motherboard above .1. Source file stored in the src directory, QII the project file stored in the directory Proj 2. Realize the functional test procedures for 4 × 4 keyboard keys specific digital keys through the board to show possession. K1 press on the display 1, K2 on the display 2. Users can try .3. Specific reference code.
Date : 2025-12-30 Size : 68kb User : Jak
[VHDL-FPGA-Verilog] VGA DL : 0: 这个试验要配合EDA4.0底板一起使用.先将核心板插在EDA4.0底板上面,然后接上VGA显示器. 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色； 3。具体设计参考代码。 -The pilot should be used in conjunction with the backplane EDA4.0. First core plate inserted EDA4.0 floor above, and then connect to VGA monitors .1. Source file stored in the src directory, QII the project file stored in the directory Proj 2. Realize the function of the procedure is displayed on the monitor in the VGA color stripes, a total of eight kinds of color 3. Specific reference code.
Date : 2025-12-30 Size : 57kb User : Jak
[VHDL-FPGA-Verilog] oc_i2c_masterI2CIP DL : 0: *** ***OC_I2C_Master使用说明*** ***** 使用步骤：1.将OC_I2C_Master文件夹拷贝到安装盘\altera\kits\nios2\components目录下。之后重新打开SOPC Builder，在可用元件列表的DeviceSOPC组中将出现OC_I2C_Master 元件，即可像其它Altera外设元件一样添加和使用。 2.hdl文件夹中包含有描述i2c逻辑的硬件描述文件，不能删除。 3.HAL文件夹包含硬件抽象层所需的文件（即驱动），不能删除。 4.inc文件夹包含有定义底层硬件的C语言头文件，不能删除. 5.I2C_doc文件夹下有关于该元件的开发文档。-********* OC_I2C_Master use*********** use these steps: 1. OC_I2C_Master folder will be copied to the installation disk alterakits ios2components directory. Re-open after the SOPC Builder, a list of available devices will appear DeviceSOPC Group OC_I2C_Master components, can be similar to other peripheral devices like Altera add and use. 2.hdl folder contains logical description i2c hardware description files, can not be deleted. 3.HAL folder contains the necessary hardware abstraction layer file (ie drivers), can not be deleted. 4.inc folder contains the definition of the underlying hardware C language header files, should not delete. 5.I2C_doc folder on the development of document components.
Date : 2025-12-30 Size : 188kb User : 姓名
[VHDL-FPGA-Verilog] MyProject DL : 0: 3-8译码器的仿真实验。本实验选用的仿真开发软件是MAX+plus II Version 9.3，原理图源文件保存在MyProject目录中，为138decoder.gdf，另有我写的实验报告，呵呵，适合仿真入门-3-8 decoder simulation. Selected in this experiment simulation software is MAX+ Plus II Version 9.3, schematic source files stored in the MyProject directory for 138decoder.gdf, otherwise I write experimental reports, Ha ha, suitable for simulation of induction
Date : 2025-12-30 Size : 219kb User : zhang
[VHDL-FPGA-Verilog] ModelSim_License DL : 2: Altera Modesim破解版的LICENCE. 下载解压后: 1.直接运行mentorkg.exe(生成的license.txt拷贝到D:\altera\80\modelsim_ae\下或者mentorkg.exe拷贝到此目录下运行). 2.设置环境变量lm_license_file="D:\altera\80\modelsim_ae\license.txt" 3.搞定-Altera Modesim cracked version of the LICENCE. Decompress after download: 1. Direct running mentorkg.exe (generated copy license.txt to the D: altera80modelsim_ae the next copy of this directory or mentorkg.exe run) .2. Lm_license_file = Set environment variables D: altera80modelsim_aelicense.txt 3. get
Date : 2025-12-30 Size : 306kb User : xingyu
[VHDL-FPGA-Verilog] 071126142104 DL : 0: system verilog This directory has all the examples in chapter 1. The examples are in different directories. The table below lists the location of hte examples.-system verilog
Date : 2025-12-30 Size : 453kb User : 张健
[VHDL-FPGA-Verilog] oc_i2c_master DL : 0: 这是一个I2C的IP。直接拷到altera公司的相应软件的目录下，即可应用。-This is an I2C of IP. Kaodao altera directly corresponding software company directory, can be applied.
Date : 2025-12-30 Size : 192kb User : 小杨
[VHDL-FPGA-Verilog] Verilog_HDL DL : 0: 华为文档《硬件描述语言Verilog基础》-目录原来搞VHDL，刚刚开始学Verilog。觉得这个入门的提纲不错，共享一下。 -Huawei Documents " basic Verilog Hardware Description Language" - the original directory engage in VHDL, just beginning to learn Verilog. Feel that the entry of the outline of a good, share some.
Date : 2025-12-30 Size : 257kb User : taotao

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