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[VHDL-FPGA-Verilog] vhdl_dial DL : 0: 拨码开关实验拨码开关8 位0 1 状态在8 位7 段数码管相应位上显示0 或1。-dial-switch dial-switching experiment 8 0 1 state in seven of the eight corresponding digital control-show or a 0.
Date : 2025-12-20 Size : 158kb User : 赵海东
[VHDL-FPGA-Verilog] Dial DL : 0: vhdl经典源代码——键盘接口设计，入门者必须掌握-vhdl classical source code-- the keyboard interface design, beginners must master
Date : 2025-12-20 Size : 721kb User : jeffery
[VHDL-FPGA-Verilog] test02 DL : 0: 用quartusII编写的，基于vhdl语言的按键加法器，从0到11，也可通过拨码开关控制，从11到0，加入了键盘防手抖。-QuartusII prepared to use, based on the VHDL language button adder, from 0-11, also available via dial code switch control, from 11-0, joined the anti-tremor keyboard.
Date : 2025-12-20 Size : 200kb User : zhg
[VHDL-FPGA-Verilog] seg7_1a DL : 0: 输入一个四位二进制数，使用拨码开关表示，使发光二极管显示这四位二进制数。-4 Enter a binary number, use the dial code switches that make light-emitting diodes show the four binary number.
Date : 2025-12-20 Size : 202kb User : fishafish
[VHDL-FPGA-Verilog] zmd_1 DL : 0: 用VHDL描述一个由8个发光二极管组成的走马灯。有系统复位。单点移动模式：一个点在8个发光二极管上来回的亮。幕布式：从中间两个点，同时向两边依次点亮直至全亮，然后再向中间点灭，依次往复。采用拨码开关转换显示模式。 -Use VHDL to describe an 8-digit LED lantern. System has reset. Single point of mobile model: a point in eight light-emitting diode on the light back and forth. Curtain-style: from between the two points, at the same time on both sides until the whole bright light followed, and then point out to the middle, followed by reciprocating. Using dial code conversion display mode switch.
Date : 2025-12-20 Size : 1kb User : wx
[VHDL-FPGA-Verilog] unsigned_4_adder DL : 0: 通过vhdl语言实现四位无符号数的加法，四位拨位置数，用数码管输出结果-Through the VHDL language realize the number of four unsigned adder, four dial location number of digital control output
Date : 2025-12-20 Size : 2kb User : 万玉龙
[VHDL-FPGA-Verilog] paobiao DL : 1: 一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
Date : 2025-12-20 Size : 43kb User : jyb
[VHDL-FPGA-Verilog] guard_against_theft DL : 0: 利用XC9572－PQ44（Xilinx CPLD）制作的一款家用防盗报警器的Verilog源代码及原理图，当房门打开后，15秒内若没有按下Key1,则会自动拨打设定手机号（当然，要另连接一台手机）-Using XC9572-PQ44 (Xilinx CPLD) produced by a home burglar alarm of the Verilog source code and the schematic diagram, when the door opened, within 15 seconds if there is no pressing Key1, will be set automatically dial the phone number (of course, Another connection to a mobile phone)
Date : 2025-12-20 Size : 897kb User : 李德明
[VHDL-FPGA-Verilog] lift DL : 0: 电梯控制程序，按钮控制电梯的上下，拨玛开关设置楼层。-Elevator control procedures of the upper and lower elevator button control, set the dial switch floors Ma.
Date : 2025-12-20 Size : 536kb User : lc
[VHDL-FPGA-Verilog] Mars_EP1C3_S_Core_V2.0 DL : 0: 此包中为Mars_EP1C3_S_Core_V2.0 FPGA学习板中的接口实验代码.共包括10个实验源代码:7段数码管,i2c,KEYSCAN,MCU,PS2,UART,VGA，蜂鸣器，跑马灯和拨码开关. -This learning package for Mars_EP1C3_S_Core_V2.0 FPGA board interface test code. A total of 10 experiments, including source code: 7 segment digital tube, i2c, KEYSCAN, MCU, PS2, UART, VGA, buzzer, marquees and dial switch.
Date : 2025-12-20 Size : 2.08mb User : wzh
[VHDL-FPGA-Verilog] yejingdeng DL : 0: 液晶时钟连线方式：将拨码开关的第6脚拨向"ON"方向，即给lcd供电-Crystal clock attachment: dial 6 feet of code switch to "ON", namely to LCD power supply
Date : 2025-12-20 Size : 13kb User : yang
[VHDL-FPGA-Verilog] VEDA7LED DL : 0: 采用QUARTUS II 7.2 (32-BIT)工具实现的两位7段数码管动态扫描显示的VHDL程序。硬件电路采用8位拨位开关控制，高四位控制左数码管，第四位控制右数码管。芯片采用EP1C6T144FPGA器件。-By QUARTUS II 7.2 (32-BIT) tools to achieve the two 7-segment digital tube dynamic scan showed the VHDL program. 8-bit hardware with dial-bit switch control, high control left four digital control, control of the right fourth digital control. Chip EP1C6T144FPGA device.
Date : 2025-12-20 Size : 435kb User : yljhs
[VHDL-FPGA-Verilog] dial DL : 0: 读入拨码开关8位0 1状态在8位7段数码管相应位上显示0或1。-Reads DIP switch 8 0 1 state in the 8-bit 7-segment display the corresponding bit 0 or 1.
Date : 2025-12-20 Size : 1kb User : riversky
[VHDL-FPGA-Verilog] bcd DL : 0: 4位二进制数转BCD码，由拨码键盘输入，结果由数码管显示-BCD 4-bit binary code switch from dial code keyboard input, the results from the digital display
Date : 2025-12-20 Size : 1kb User : riversky
[VHDL-FPGA-Verilog] coded-lock DL : 0: 设计的是一个保险柜的数字锁控制电路。首先最主要的问题是安全，也就是开锁的密码被破译的可能性要尽可能小；其次是操作方便，开锁的程序不过于复杂。此外还有一些特殊要求，例如可预置和更改密码，多次输入错误密码应启动报警系统，使用者在拨错号码时可将原拨号码清除重拨，段码显示等。-Design is a digital safe lock control circuit. First, the main problem is security, that is unlocking the password is likely to crack as small as possible followed by ease of operation, unlocking procedure but in the complex. There are also some special requirements, such as preset and change the password, enter the wrong password several times should start alarm system, the user dialed the wrong number dial the number when the original clear redial, segment display, etc..
Date : 2025-12-20 Size : 119kb User : 张洁
[VHDL-FPGA-Verilog] phone DL : 0: 模仿电话拨号，并且有晶体管显示输入的数字-Imitation of dial-up, and there are number of transistors display input
Date : 2025-12-20 Size : 1kb User : jiangyan
[VHDL-FPGA-Verilog] Dial DL : 0: 简单的拨码盘实验设计，从拨码盘读数显示在数码管上，供初学者参考。-Simple dial encoder experimental design, reading from a dial code displayed on the digital disc, the reference for beginners.
Date : 2025-12-20 Size : 681kb User : Domo
[VHDL-FPGA-Verilog] Encoder4_2 DL : 0: Encoder4_2，带优先级的编码器此实验完成但优先级的4-2编码，以拨动开关SW[3..0]作为输入源（开关上拨时输入为高电平），其中SW[3]的优先级高于SW[2]的优先级，SW[2]的优先级高于SW[1]的优先级，以此类推。编码的结果会以LED灯的形式显示。例如，当SW[2]上拨而SW[3]没有上拨时，LED[1..0]的显示结果将是“10”。-Encoder4_2, with a priority encoder to complete this experiment, but the 4-2 priority encoder to toggle switch SW [3 .. 0] as the input source (input switch is high on the dial), which SW [3 ] takes precedence over the SW [2] priority, SW [2] takes precedence over the SW [1] priority, and so on. The results will be encoded in the form of LED lights display. For example, when the SW [2] on the dial and the SW [3] When not on call, LED [1 .. 0] to display the result will be " 10."
Date : 2025-12-20 Size : 209kb User : 王晨
[VHDL-FPGA-Verilog] FPGAxinlingyinfangzhen DL : 0: 基于FPGA的信令音产生程序，包括拨号音，忙音，振铃音等-FPGA-based signaling tone generation process, including dial tone, busy tone, ring tones, etc.
Date : 2025-12-20 Size : 2.03mb User : 于风
[VHDL-FPGA-Verilog] dial DL : 0: verilog 写的v5板子按键的测试程序可以直接使用已测试-this is a code applied for dial in v5
Date : 2025-12-20 Size : 1kb User : 谢景磊

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