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[VHDL-FPGA-Verilog] 3-8译码器 DL : 0: vhdl的3-8译码器-instantiate the 3-8 decoder
Date : 2025-12-25 Size : 976kb User : 熊辉波
[VHDL-FPGA-Verilog] Viterbidecoder DL : 0: 维特比解码器低功耗设计verilog编码完整的程序可直接用-Viterbi decoder low power design Verilog coding complete procedures can be used directly
Date : 2025-12-25 Size : 377kb User : 杨艺
[VHDL-FPGA-Verilog] decode_for_m68008 DL : 0: -- M68008 Address Decoder -- Address decoder for the m68008 -- asbar must be 0 to enable any output -- csbar(0) : X"00000" to X"01FFF" -- csbar(1) : X"40000" to X"43FFF" -- csbar(2) : X"08000" to X"0AFFF" -- csbar(3) : X"E0000" to X"E01FF" -- download from www.pld.com.cn & www.fpga.com.cn --- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn
Date : 2025-12-25 Size : 1kb User : 罗兰
[VHDL-FPGA-Verilog] 1553_enc_dec DL : 0: 1553B的编解码程序很好用给大家分享 -the series 1553B decoder procedure is useful for everyone to share share
Date : 2025-12-25 Size : 31kb User : 黄名
[VHDL-FPGA-Verilog] tcm_decode DL : 0: TCM解码，VHDL代码，是我在工作中做的工程代码，时序稳定，里面有syn以及软判决的算法，经典-TCM decoder, VHDL code, yes, I do work in the project code, timing stability, There are syn and soft-decision algorithm, classic!
Date : 2025-12-25 Size : 19kb User : 刘超
[VHDL-FPGA-Verilog] decoder(vhdl) DL : 0: 这是用VHDL编写的译码程序,程序简单易懂-VHDL prepared decoding procedures that are simple to understand
Date : 2025-12-25 Size : 105kb User : 黄鹏飞
[VHDL-FPGA-Verilog] AEScoremodules DL : 0: AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Date : 2025-12-25 Size : 10kb User : 许茹芸
[VHDL-FPGA-Verilog] 8b10b_Decoder DL : 0: 应用VHDL设计的8b10b解码器源文件，实现高速的串行数据传输。-application VHDL design 8b10b decoder source, the realization of high-speed serial data transmission.
Date : 2025-12-25 Size : 18kb User :
[VHDL-FPGA-Verilog] RS(32to28)encoderanddecoder DL : 1: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Date : 2025-12-25 Size : 75kb User : 王文
[VHDL-FPGA-Verilog] 38decoder DL : 0: 使用Verilog硬件描述语言编程的38译码器，包含测试描述-Using Verilog hardware description language programming decoder 38 contains the test description
Date : 2025-12-25 Size : 68kb User : sss
[VHDL-FPGA-Verilog] bch_encoder_decoder DL : 0: bch encoder+decoder 源代码，Flash控制器，通讯都需要用到哦-bch encoder+ decoder source code, Flash controller, communications are needed Oh
Date : 2025-12-25 Size : 133kb User : linchan
[VHDL-FPGA-Verilog] viterbi DL : 0: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Date : 2025-12-25 Size : 61kb User : yaoyongshi
[VHDL-FPGA-Verilog] mancheester_v DL : 1: 用Verilog HDL实现的曼彻斯特编码器和解码器。-Using Verilog HDL realize the Manchester encoder and decoder.
Date : 2025-12-25 Size : 9kb User : wangyunshann
[VHDL-FPGA-Verilog] VHDL DL : 1: VHDL程序集锦，很多有用程序，英文版其中有汉明码编译码，优先译码等等。-VHDL Collection procedures, many useful procedures, the English version of them hamming code encoding and decoding, the priority decoder and so on.
Date : 2025-12-25 Size : 165kb User : 萍果
[VHDL-FPGA-Verilog] RS(204_188)decoder DL : 0: <Verilog HDL 语言编程》 RS(204,188)译码器的设计-<Verilog HDL language programming RS (204,188) Decoder
Date : 2025-12-25 Size : 11kb User : 李映波
[VHDL-FPGA-Verilog] RS(31-19-6) DL : 0: reed-solomon译码器。共有7个文件，分别为译码器的7个模块。-reed-solomon decoder. A total of seven papers, respectively, the decoder module 7.
Date : 2025-12-25 Size : 9kb User : liwei
[VHDL-FPGA-Verilog] Decoder DL : 0: 这是一个HDB3的译码器，实现从HDB3双极性码到高低电平二值序列的转化-This is a decoder of the HDB3, HDB3 bipolar from high-low-level code to the conversion of binary sequences
Date : 2025-12-25 Size : 1kb User : 石云
[VHDL-FPGA-Verilog] decoder DL : 0: 一个verilog源代码，用于译码器的编程。-A verilog source code, for programming decoder.
Date : 2025-12-25 Size : 64kb User : PUDN_CHEN
[VHDL-FPGA-Verilog] decoder DL : 0: 指令译码器的设计vhdl语言或者verilog HDL语言对单片机程序的处理-Instruction decoder design vhdl language or verilog HDL language processing microcomputer programs
Date : 2025-12-25 Size : 1kb User : wvqyd
[VHDL-FPGA-Verilog] Program of 2 to 4 Decoder DL : 0: Verilog code for decoder
Date : 2025-12-25 Size : 9kb User : maz1

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