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[VHDL-FPGA-Verilog] 并口的CPLD烧录线，通过跳线支持三大厂家的CPLD/FPGA(Altera,Xilinx,Lattice) DL : 2: 并口的CPLD烧录线，通过跳线支持三大厂家(Altera,Xilinx,Lattice)的CPLD/FPGA烧录,附有电路图与Verilog HDL文档.使用的芯片为XC9572XL-VQ64
Date : 2010-10-14 Size : 2.2mb User : mikeldm@163.com
[VHDL-FPGA-Verilog] CPLD 與 61LV256 SRAM 驱动 TFT DL : 0: CPLD 與 61LV256 SRAM 驱动 4.3 吋的 TFT,附 Verilog 語言範例.
Date : 2011-06-28 Size : 2.83kb User : xyz543
[VHDL-FPGA-Verilog] 用VHDL语言在CPLD上实现串行通信 DL : 0: 用VHDL语言在CPLD上实现串行通信-using VHDL on the CPLD Serial Communication
Date : 2025-12-19 Size : 4kb User : 陈旭
[VHDL-FPGA-Verilog] 终端CPLD逻辑工程文件 DL : 0: 该工程文件实现ARM系统中CPLD的逻辑工作，起到外围资源的逻辑地址译码功能-realization of the project document ARM system CPLD logic, external resources have address decoding logic function
Date : 2025-12-19 Size : 115kb User : 王希
[VHDL-FPGA-Verilog] cpld DL : 0: cpld与单片机接口设计,利于电子设计及应用- Interface design between microprocessor and cpld ,suit for IC design and application
Date : 2025-12-19 Size : 8kb User : 宋健
[VHDL-FPGA-Verilog] CPLD的跑馬燈 DL : 0: cpld的入门交流：CPLD的跑馬燈一个简易型cpld试验电路用VHDL语言遍的-cpld entry exchange : CPLD 5,250 cpld an easy-to-use test circuit using VHDL times the
Date : 2025-12-19 Size : 63kb User : 口是心非
[VHDL-FPGA-Verilog] 用cpld实现曼彻斯特编码 DL : 0: 用cpld实现曼彻斯特编码用verilog HDL进行曼彻斯特编码，用于通信中-cpld achieve with Manchester encoding with Verilog HDL Manchester encoding. for Communication
Date : 2025-12-19 Size : 4kb User : 李鹏
[VHDL-FPGA-Verilog] cpld-download-cable-tuzi DL : 0: cpld下载电缆的详细图纸及说明，244实现，稳定，速度不错。-cpld download cable detailed drawings and descriptions, 244 realization, stable, good speed.
Date : 2025-12-19 Size : 4.09mb User : mengzi
[VHDL-FPGA-Verilog] CPLD-AT89C51com DL : 0: 可编程逻辑器件cpld与单片机双向通信的源程序-Programmable logic device CPLD and MCU for two-way communication of the source
Date : 2025-12-19 Size : 1kb User : jjaai
[VHDL-FPGA-Verilog] CPLD DL : 0: 汽车四轮定位CCD驱动CPLD源代码，支持toshiba tcd1209d-Four-wheel drive car CCD positioning CPLD source code, support for toshiba tcd1209d
Date : 2025-12-19 Size : 196kb User : 徐磊
[VHDL-FPGA-Verilog] Cpld DL : 0: atmel公司arm926 开发办cpld源代码vhdl写的，供大家参考-Atmel CPLD Development Office Company ARM926 VHDL source code written for your information
Date : 2025-12-19 Size : 38kb User : 邱劲松
[VHDL-FPGA-Verilog] cpld-pwm DL : 0: 基于cpld的pwm控制设计采用vhdl.verilog语言设计对大家比较有用-CPLD-based control design uses the pwm design vhdl.verilog language more useful for everyone
Date : 2025-12-19 Size : 78kb User : emily
[VHDL-FPGA-Verilog] cpld DL : 0: 基于CPLD XC95018开发的一段VHDL代码，可实现多个8051单片机互相通讯，对多单片机系统的设计很有参考价值-Based on CPLD XC95018 developed section of VHDL code, can realize more than 8051 mutual communication, single-chip microcomputer system for the design of multi-reference value is
Date : 2025-12-19 Size : 886kb User : 蔡彬彬
[VHDL-FPGA-Verilog] CPLD-CRACK-SIEMENS-200PLC DL : 2: 可用来破解分析西门子200 PLC与模块的通讯协议，基于ALTERA CPLD EPM240的设计. 需要配合分析板配套使用。-Analysis can be used to crack the Siemens 200 PLC and the communication protocol modules, based on the ALTERA CPLD EPM240 design. The need to tie in with the analysis supporting the use of panels.
Date : 2025-12-19 Size : 2kb User : wuzhen
[VHDL-FPGA-Verilog] cpld DL : 0: 基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集原码开发软件 Quartus II -ATEREAL EPM1270T144C5N CPLD-based pressure sensor data acquisition source Quartus II development software
Date : 2025-12-19 Size : 301kb User : 胡兵
[VHDL-FPGA-Verilog] cpld DL : 0: CPLD VHDL 数码管程序流水灯程序时钟程序 -CPLD VHDL program LED lights water clock procedures procedures CPLD VHDL program LED lights process water clock procedures
Date : 2025-12-19 Size : 465kb User : 朱工
[VHDL-FPGA-Verilog] VerilogHDL-and-CPLD-programming-technology DL : 0: 从零开始学CPLD和VerilogHDL编程技术，包括实验板原理图和实验源代码。-VerilogHDL learn from scratch and CPLD programming technologies, including board schematics and test source code.
Date : 2025-12-19 Size : 3.02mb User : 宋大力
[VHDL-FPGA-Verilog] CPLD DL : 0: 天祥视频中的所有程序，希望能对爱好CPLD编程的人有所帮助-Tienhsiang video in all programs, hoping to those who love CPLD programming help
Date : 2025-12-19 Size : 734kb User : 漫漫
[VHDL-FPGA-Verilog] counter-CPLD DL : 0: CPLD学习，用VHDL,应用EPM7032,一个138，373和273的例程-CPLD study, using VHDL, application EPM7032, one of the routines 138,373, and 273
Date : 2025-12-19 Size : 98kb User : YAN
[VHDL-FPGA-Verilog] UART-CPLD DL : 0: 使用VHDL在CPLD上设计UART的一个项目-VHDL design UART
Date : 2025-12-19 Size : 6.01mb User : yuyue

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