Search - compress on-the-fly

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[VHDL-FPGA-Verilog] jpeg.tar DL : 0: This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is not limited. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image. Its quality is comparable to software solutions.
Date : 2026-01-09 Size : 3.26mb User : Bill Guan