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[VHDL-FPGA-Verilog] 数字锁相环设计源程序 DL : 0: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Date : 2025-12-19 Size : 118kb User : 杰轩
[VHDL-FPGA-Verilog] DesignCompiler DL : 0: Design Compiler使用简要说明,说明了用这一工具进行综合的过程 -use Design Compiler brief statement, the use of this tool for integrated process
Date : 2025-12-19 Size : 1.25mb User : qindao
[VHDL-FPGA-Verilog] SPI_verilogHDL DL : 0: 本原码是基于Verilog HDL语言编写的，实现了SPI接口设计，可以应用于FPGA,实现SPI协议的接口设计.在MAXII编译成功,用Modelsim SE 6仿真成功.-primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI interface design. MAXII success in the compiler, Modelsim SE with six successful simulation.
Date : 2025-12-19 Size : 1kb User : jevidyang
[VHDL-FPGA-Verilog] 9.2_LCD_PULSE DL : 0: 基于Verilog-HDL的硬件电路的实现 9.2 具有LCD显示单元的可编程单脉冲发生器　　9.2.1 LCD显示单元的工作原理　　9.2.2 显示逻辑设计的思路与流程　　9.2.3 LCD显示单元的硬件实现　　9.2.4 可编程单脉冲数据的BCD码化　　9.2.5 task的使用方法　　9.2.6 for循环语句的使用方法　　9.2.7 二进制数转换BCD码的硬件实现　　9.2.8 可编程单脉冲发生器与显示单元的接口　　9.2.9 具有LCD显示单元的可编程单脉冲发生器的硬件实现　　9.2.10 编译指令-"文件包含"处理的使用方法 -based on Verilog-HDL hardware Circuit of 9.2 LCD display module with the series Single-Pulse Generator 9.2.1 LCD display module Principle 9.2.2 shows the logic design Thinking and Process 9.2.3 LCD display module hardware 9.2.4 programmable single pulse data BCD of the task 9.2.5 9.2.6 for the use of the phrase cycle use 9.2.7 binary conversion of BCD programmable hardware 9.2.8 single pulse generator with a said unit 9.2.9 interface with the LCD display module programmable pulse generator hardware 9 .2.10 compiler directives- "document includes" the use of
Date : 2025-12-19 Size : 5kb User : 宁宁
[VHDL-FPGA-Verilog] 9.7_DIRIVER_control DL : 1: 基于Verilog-HDL的硬件电路的实现 9.7 步进电机的控制　　9.7.1 步进电机驱动的逻辑符号　　9.7.2 步进电机驱动的时序图　　9.7.3 步进电机驱动的逻辑框图　　9.7.4 计数模块的设计与实现　　9.7.5 译码模块的设计与实现　　9.7.6 步进电机驱动的Verilog-HDL描述　　　9.7.7 编译指令-"宏替换`define"的使用方法　　9.7.8 编译指令-"时间尺度`timescale"的使用方法　　9.7.9 系统任务-"$finish"的使用方法　　9.7.10 步进电机驱动的硬件实现 -based on Verilog-HDL hardware Circuit of 9.7 Stepper Motor Control 9.7 .1 stepper motor-driven logic symbols 9.7.2 stepper motor driven map the chronology-- Step 9.7.3 Machine-driven logic diagram 9.7.4 Counting Module Design and Implementation 9.7.5 decoding module design and Implementation 9.7.6 stepper motor driven Verilog-HDL Compiler means locale 9.7.7 Description Order- "macro substitution` define "the use 9.7.8 compiler directives-" The time scale `tim escale "use 9.7.9 system tasks-" $ finish "to use 9.7.10 stepper motor drive hardware
Date : 2025-12-19 Size : 2kb User : 宁宁
[VHDL-FPGA-Verilog] Quartus_vhdl DL : 0: 用QUARTUS编译通过的等精度频率计，我错误，但有几个警告（不影响设计）。我的毕业设计啊！！！ -QUARTUS used by the compiler, and other precision frequency, I am wrong. But there are several warning (not affect design). I graduated from the design ah! ! !
Date : 2025-12-19 Size : 43kb User : 刘刚
[VHDL-FPGA-Verilog] CompilerOptimizations DL : 0: To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.
Date : 2025-12-19 Size : 51kb User : zhangyg
[VHDL-FPGA-Verilog] VideoGenerator DL : 0: 用lattice XP3 demo板设计的VGA信号发生器，编译平台ispLEVER6-With lattice XP3 demo board design VGA signal generator, the compiler platform ispLEVER6
Date : 2025-12-19 Size : 287kb User : 朱强光
[VHDL-FPGA-Verilog] trafficwsdklk DL : 0: １．设计目的（１）设计交通灯控制器；（２）学习状态机的设计方法；（３）学习原理图、状态机等多种的设计方法进行混合设计；（４）熟练掌握器件设计输入、编译、仿真和编程的过程。２．设计内容位于十字路口的交通灯，在A方向和B方向各有红、黄、绿三盏灯，按所列顺序进行循环，交通灯循环顺序见表1所示。其中1表示灯亮，0表示灯灭。 -1. Designed to (1) design of traffic signal controllers (2) study the design method of state machine (3) learning principle diagram, state machine design methods such as mixed design (4) proficiency in the design of input devices, the compiler , simulation and programming process. 2. Design the content of the traffic lights at a crossroads, in the A direction and B direction of each of red, yellow and green three lights, according to the order listed in the cycle, the traffic light cycle sequence in Table 1 below. 1 said lights, said lights out 0.
Date : 2025-12-19 Size : 129kb User : 秦光
[VHDL-FPGA-Verilog] jiaotongdeng DL : 0: 交通灯VHDL设计，所有程序和顶层逻辑图都有，编译已通过，管脚分配可按实际分配-VHDL design of traffic lights, all the procedures and have a top-level logic diagram, the compiler has passed, according to the actual distribution of pin allocation
Date : 2025-12-19 Size : 229kb User : zhang
[VHDL-FPGA-Verilog] uart DL : 0: VHDL编写的异步通信串行口设计用Quartus工具编译-VHDL prepared the design of serial asynchronous communication tool used Quartus compiler
Date : 2025-12-19 Size : 208kb User : 朱兆斌
[VHDL-FPGA-Verilog] FPGA DL : 0: FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE 第一章 Modelsim编译Xilinx库第二章调用Xilinx CORE-Generator 第三章使用Synplify.Pro综合HDL和内核第四章综合后的项目执行第五章不同类型结构的仿真-FPGA design of the whole process: Modelsim>> Synplify.Pro>> ISE Chapter ModelSim Xilinx compiler library chapter called Xilinx CORE-Generator Chapter III Synplify.Pro integrated use of Chapter IV of HDL and kernel integrated implementation of the project after the Chapter V structure of different types of simulation
Date : 2025-12-19 Size : 213kb User : 青岚之风
[VHDL-FPGA-Verilog] Random_Number_generator DL : 0: 此代码用于产生系统设计仿真阶段需要的仿真数据，运行的结果是一系列随机数。编译后可生成数据产生模块，在其他工程中之间调用之作为数据输入即可，对vhdl涉及仿真有一定的帮助-This code is used for creating a system design simulation stage of simulation data, the results of running a series of random numbers. Compiler can generate data generated modules, in other works as a call between the data input to the VHDL simulation involves a certain degree of help
Date : 2025-12-19 Size : 35kb User : 王弋妹
[VHDL-FPGA-Verilog] led DL : 0: 8位数码扫描显示电路设计（VHDL）通过编译-8 digital scanning display circuit design (VHDL) through compiler
Date : 2025-12-19 Size : 1kb User : hh
[VHDL-FPGA-Verilog] ALU DL : 0: vhdl代码使用quartus编译 cpu中 alu的设计可作为课程设计的参考此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
Date : 2025-12-19 Size : 1kb User : 闵瑞鑫
[VHDL-FPGA-Verilog] ebook_verilog_fine_state_machine DL : 0: Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world examples.
Date : 2025-12-19 Size : 119kb User : rex
[VHDL-FPGA-Verilog] alu DL : 0: 设计带进位算术逻辑运算单元，根据74LS181功能表，用Verilog HDL硬件描述语言编程实现ALU181的算术逻辑运算功能，编辑实验原理图，在算术逻辑单元原理图上，将其扩展为带进位的算术逻辑运算单元，对其进行编译，并设计波形对其进行仿真验证，最后下载验证-Design into the digital arithmetic logic operation unit, in accordance with menu 74LS181 with Verilog HDL hardware description language programming ALU181 function arithmetic logic operations, editing Experimental schematic diagram, in the Arithmetic Logic Unit schematic diagram on its expansion into the spaces for arithmetic logic operation unit, its compiler, and the design of their simulation waveforms, and finally download the verification
Date : 2025-12-19 Size : 652kb User : 623902748
[VHDL-FPGA-Verilog] ASIC_Design_Flow_Tutorial_with_synopsys DL : 0: Tutorial from VCS to IC Compiler for ASIC design using synopsys tool. .
Date : 2025-12-19 Size : 3.94mb User : Kang
[VHDL-FPGA-Verilog] 4Day DL : 0: 《4天学会Design Compiler》的中文版。《4天学会Design Compiler》大家都该知道的，一个很好的DC入门教才，我也是学习时找到了这个中文版。《4天学会Design Compiler》可以在xunlei上下载到。-" 4-day Institute of Design Compiler" the Chinese version. " 4-day Institute of Design Compiler" Everyone in the know, a good DC to teach entry-only, I also found this when studying Chinese. " 4-day Institute of Design Compiler" can be downloaded to xunlei.
Date : 2025-12-19 Size : 591kb User : 唐霖
[VHDL-FPGA-Verilog] fir_compiler DL : 0: FIR编译器。自动生成具有用户自定参数的FIR滤波器。在 matlab里面设计滤波器，matlab里面设计输入字长。生成的rtl代码是该文件的头部有位宽宏定义，可以自行查阅。 -FIR Compiler. Automatically generate a user-defined parameters of FIR filters. Design a filter inside the matlab, matlab which design input word length. Rtl code is generated by the head of the document there was a generous definition, self-inspection.
Date : 2025-12-19 Size : 2.04mb User : 秋田

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