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[VHDL-FPGA-Verilog] 数字锁相环设计源程序 DL : 0: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Date : 2025-12-21 Size : 118kb User : 杰轩
[VHDL-FPGA-Verilog] 4x4的数据选择器 DL : 0: 用vhdl的4x4的数据选择器，在maxplusII下编译、仿真通过。是构成大型数字电路的重要部件。适合vhdl初学者分析学习。-4x4 with the VHDL data selectors, under the maxplusII compiler, simulation through. Yes constitute large-scale digital circuits important components. VHDL Analysis for beginners to learn.
Date : 2025-12-21 Size : 3kb User : roya
[VHDL-FPGA-Verilog] USB枚举 DL : 0: ALTERA　NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口-Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface
Date : 2025-12-21 Size : 35kb User : xf
[VHDL-FPGA-Verilog] SRAM@DMA实验 DL : 0: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Date : 2025-12-21 Size : 33kb User : xf
[VHDL-FPGA-Verilog] SPI接口音频Codec实验 DL : 0: ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
Date : 2025-12-21 Size : 34kb User : xf
[VHDL-FPGA-Verilog] 一个8位CISC结构的精简CPU DL : 0: 一个8位CISC结构的精简CPU，2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler
Date : 2025-12-21 Size : 92kb User : 陈旭
[VHDL-FPGA-Verilog] Digital_030423 DL : 0: 服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).-server board controller is contained in the AHDL procedures, including schematic compiler, the use EPM7128 (CPLD).
Date : 2025-12-21 Size : 514kb User : 老罗
[VHDL-FPGA-Verilog] fifo数据缓冲器的vhdl源程序 DL : 0: 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-Bianlegan 8* 8 of the data buffer fifo VHDL source, after quartusII4.2 compiler successful procedures. . Hope you enjoy the exchanges
Date : 2025-12-21 Size : 1kb User : 夏社
[VHDL-FPGA-Verilog] 脉冲记时CPLD DL : 0: 工作原理：脉冲输入，记录30个脉冲的间隔时间（总时间），LED显示出来，牵涉到数码管的轮流点亮，以及LED的码。输入端口一定要用个 74LS14整一下，图上没有。数码管使用共阴数码管。MAXPLUS编译。测试时将光电门的信号端一块连接到J2口的第三管脚，同时第一管脚为地，应该与光电门的地连接（共地）。开始测试：按下按键，应该可以见到LED被点亮，指示可以开始转动转动惯量盘，等遮光片遮挡30次光电门后， LED熄灭，数码管有数字显示，此为时间值，单位为秒，与智能计时器的连续脉冲测试模式中的T30值进行比较。再按下按键即可进行下一次测量。水平有限，见笑。-principle : pulse input, recording 30 pulse interval (total time), the LED display and digital control involves rotating lights, and LED yards. Input port must use the entire 000 74LS14 that there is no map. Digital control the use of digital control were overcast. Segments compiler. Test the door to the photoelectric signal an end connected to the mouth of the third J2 pins, for the first pin, should the photoelectric doors to connect (to a total). Testing : press the button, should be able to see the LEDs are lit, instructions to start the rotation inertia set, films such as shading block 30 photoelectric doors, the LED is off, digital possession figures show that for the time value of this unit for seconds Intelligent timer with a continuous pulse mode testing of T30 values were compare
Date : 2025-12-21 Size : 630kb User : 高颖峰
[VHDL-FPGA-Verilog] 66_FIR DL : 0: 这是一个VHDL写的FIR模块，我的编译环境是QuartusII 5.0-This is a VHDL modules written FIR, I compiler environment is Quartus II 5.0
Date : 2025-12-21 Size : 8kb User : 佴立峰
[VHDL-FPGA-Verilog] key_scan1 DL : 0: 用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功-achieved using Verilog 4 x 4 keyboard procedures, the Quartus II compiler on the adoption and successful
Date : 2025-12-21 Size : 581kb User : 大圣
[VHDL-FPGA-Verilog] DesignCompiler DL : 0: Design Compiler使用简要说明,说明了用这一工具进行综合的过程 -use Design Compiler brief statement, the use of this tool for integrated process
Date : 2025-12-21 Size : 1.25mb User : qindao
[VHDL-FPGA-Verilog] CompilerOptimizations DL : 0: To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.
Date : 2025-12-21 Size : 51kb User : zhangyg
[VHDL-FPGA-Verilog] XC9536XL DL : 0: 通用FPGA CPLD下载电缆的XC9536XL编译程序-Universal FPGA CPLD download cable XC9536XL compiler
Date : 2025-12-21 Size : 4kb User :
[VHDL-FPGA-Verilog] mmcfpgaconfig.tar DL : 0: 基于FPGA的MMC卡实现，内部包含了C++仿真调试代码以及FPGA的实现代码，建立工程后可以之间编译调试-FPGA-based MMC card, Internal contains C++ Simulation debugging code, as well as the realization of FPGA code, the establishment of the project can be between the compiler debugging
Date : 2025-12-21 Size : 7kb User : 王弋妹
[VHDL-FPGA-Verilog] ebook_verilog_fine_state_machine DL : 0: Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world examples.
Date : 2025-12-21 Size : 119kb User : rex
[VHDL-FPGA-Verilog] ASIC_Design_Flow_Tutorial_with_synopsys DL : 0: Tutorial from VCS to IC Compiler for ASIC design using synopsys tool. .
Date : 2025-12-21 Size : 3.94mb User : Kang
[VHDL-FPGA-Verilog] fir_compiler DL : 0: FIR编译器。自动生成具有用户自定参数的FIR滤波器。在 matlab里面设计滤波器，matlab里面设计输入字长。生成的rtl代码是该文件的头部有位宽宏定义，可以自行查阅。 -FIR Compiler. Automatically generate a user-defined parameters of FIR filters. Design a filter inside the matlab, matlab which design input word length. Rtl code is generated by the head of the document there was a generous definition, self-inspection.
Date : 2025-12-21 Size : 2.04mb User : 秋田
[VHDL-FPGA-Verilog] verilog-compiler DL : 0: 本文包含了几个关于Verilog的编译器的源码实现，适用于深入学习Verilog的读者-This article contains several Verilog compiler source for in-depth study of Verilog reader
Date : 2025-12-21 Size : 2.64mb User : 真诚的猪
[VHDL-FPGA-Verilog] minicpu(compiler-8bit) DL : 0: CISC microprocessor IP core & 8 bit compiler, verilog语言编写，可在FPGA和CPLD上综合实现,结构类似Intel 8085-CISC microprocessor IP core and 8-bit compiler, verilog language, FPGA and CPLD comprehensive realization .structure is similar to Intel 8085
Date : 2025-12-21 Size : 102kb User : gingercorn

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