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[VHDL-FPGA-Verilog] canny_edge_detector_latest.tar DL : 0: Canny edge detector with a 9x9 mask
Date : 2025-12-22 Size : 541kb User : tjayaprakash
[VHDL-FPGA-Verilog] CANNY DL : 0: 对特定图片进行canny边缘检测。首先是高斯模糊，然后sobel算子处理，再局部极大值确定，最后阈值判断。(Canny edge detection for a particular picture. The first is the Gauss fuzzy, and then the Sobel operator is processed, and then the local maximum is determined, and finally the threshold is judged.)
Date : 2025-12-22 Size : 7kb User : TonytheGreat