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[VHDL-FPGA-Verilog] Contrl_MV DL : 0: 心电图机中1MV定标电路的VHDL代码，可以实现-ECG 1mV calibration circuit VHDL code can be achieved
Date : 2025-12-22 Size : 2kb User : 黄建
[VHDL-FPGA-Verilog] 1 DL : 0: 基于VHDL语言的汉明码的译码，含有校正子跟纠错检错功能-Based on the VHDL language decoding Hamming Code, which contains sub-calibration error with error correction function
Date : 2025-12-22 Size : 3kb User : Hargie
[VHDL-FPGA-Verilog] alarm DL : 0: （1）：最基本的时间设定与校准功能；（2）：闹钟定时功能，以及闹钟响铃功能；（3）：一定条件下可以实现闹钟的时间自动修改功能；（4）：当前时间为整点时实现整点报时功能。（5）：定时显示与计时显示可以实现任意切换 -(1): the most basic function of time for setup and calibration (2): clock timing, as well as the ringing alarm clock function (3): under certain conditions, the time clock can be achieved automatically modify function (4): current time the whole point timekeeping function to bring the whole point. (5): from time to time display and time display can switch back and forth
Date : 2025-12-22 Size : 1kb User : xiaodaselang
[VHDL-FPGA-Verilog] c_xapp851 DL : 1: 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes the Virtex ™ -5 devices to achieve 200 MHz DDR SDRAM (JEDEC DDR400 (PC3200) standard) controller. The Design and Implementation of the use of IDELAY unit to adjust read data timing. Reading the data calibration and adjust the timing for completion of this controller.
Date : 2025-12-22 Size : 399kb User : 陈阳
[VHDL-FPGA-Verilog] VHDL DL : 1: （1）用VHDL语言编写程序，在EDA实验板上实现（2）能正常计时。显示模式分为两种，即24小时制和12小时制。其中12小时制须显示上，下午（用指示灯显示）。时，分，秒都要显示。（3）. 手动校准电路。用一个功能选择按钮选择较时，分功能，用另一个按钮调校对应的时和分的数值。用VHDL语言编写程序，在EDA实验板上实现（4）整点报时。（5）. 闹钟功能。（6）．秒表功能。-(1) using VHDL language program, in the EDA experiments on-board implementation (2) to resume normal time. Display mode is divided into two kinds, namely, a 24-hour system and 12-hour clock. Including 12-hour clock to be displayed on the afternoon (with light display). Hours, minutes and seconds to be displayed. (3). Manual calibration circuit. With a select button to choose a more functional hours, minutes functions, with another button to adjust the corresponding time and sub-values. Using VHDL language programs, in the EDA experiments on-board implementation (4) The whole point timekeeping. (5). Alarm. (6). Stopwatch function.
Date : 2025-12-22 Size : 4kb User : malon
[VHDL-FPGA-Verilog] digital_frequence_counter DL : 0: 设计功能： 1．.用VHDL完成12位十进制数字频率计的设计及仿真。 2．频率测量范围：1Hz∼ 10KHz，分成两个频段，即1∼ 999Hz，1KHz∼ 10KHz，用三位数码管显示测量频率，用LED显示表示单位，如亮绿灯表示Hz，亮红灯表示KHz。 3．具有自动校验和测量两种功能，即能用标准时钟校验、测量精度。 4．具有超量程报警功能，在超出目前量程档的测量范围时，发出灯光和音响信号。 -Design features: 1. . Complete with VHDL 12-bit decimal digital frequency meter design and simulation. 2. Frequency Range: 1Hz ~ 10KHz, divided into two bands, namely, 1 ~ 999Hz, 1KHz ~ 10KHz, with three digital display measuring frequency, with LED display that unit, such as the green light that Hz, red light, said KHz. 3. Calibration and measurement with automatic two functions, namely, the clock can use the standard calibration, measurement accuracy. 4. Super-range alarm function, beyond the scope of the present range of measurement files, the issue of light and sound signals.
Date : 2025-12-22 Size : 22kb User : 八毛
[VHDL-FPGA-Verilog] UHF-RFID-CRC DL : 0: 本文首先研究了IsO／IECl8000．6标准中A、B两类短程通讯的前向链路与返回链路的数据编码方式，对(FMO)双相间隔编码、(PIE)脉冲间隔编码、曼切斯特码的编解码方式和技术参数进行了深入的分析，并利用FPGA实验平台对这三种编码的编、解码电路进行了设计和仿真。然后对UHF RFID系统的差错控制技术原理进行了探讨，重点研究了ISo／IECl8000．6标准中采用的数据保护与校验技术，即循环冗余校验(CRC)技术。分析了基于线性反馈移位寄存器(LFSR)实现CRC的电路，从理论和实现两个方面对其中存在的问题提出了解决办法，设计了一种改进型线性反馈移位寄存器电路来实现循环冗余校验。对于要求CRC运算速度高的系统，本文利用了递归的算法设计了一种新型的并行CRC电路。最后本文提出了一种新颖的UHF RFID系统数字基带电路，区别于一般数字基带电路的地方是：在编解码模块和CRC模块之间加入了卷积编码和维特比译码模块。利用卷积码优良的纠错能力，来解决UHF RFID系统在电磁干扰严重的环境中识别率低、通信速度慢的问题，效果良好。-The first，this paper investigates the f．0rward link and retum link data encodlng method in short range communication types A and B in ISO／IEC 1 8000-6，and deeply analyzes encoding method and technical parameters of Bi—Phase Space(FMO)coding， Pulse IntervaI Encoding(PIE)coding and Manchester coding．We also designed and simulated code circuits and decode circuits of the three encoding method by FPGA experiment platfoml． The second， We discussed the technical principle of error control of the UHF RFID system，especially for the techn0109y of data Verification 肌d calibration，namely cyclic redundancy check that used in IS0／IEC 1 8000·6·The circuits of CRC based on Linear Feedback Shin Register(LSFR)are analyzed行om theonr and realization，and some means of solVing problems are put fon)Irard，then an improved LSFR circuit to implement CRC is designed．For some require fast CRC calculation system，we designed a noVel parallel CRC circuit by using recurslVe fomlula．In the end，we put forw
Date : 2025-12-22 Size : 4.16mb User : HY jian
[VHDL-FPGA-Verilog] DDR-SDRAM DL : 0: 本应用指南描述了在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。该实现运用了直接时钟控制技术来实现数据采集，并采用自动校准电路来调整数据线上的延迟。-This application note describes a Virtex ™ -4 XC4VLX25 FF668-10C to implement the DDR SDRAM device controller. The clock control to achieve use of technology to achieve direct data acquisition, and automatic calibration circuit to adjust the data in line delay.
Date : 2025-12-22 Size : 53kb User : syf
[VHDL-FPGA-Verilog] rcrc16 DL : 0: rcrc16的反校验码，用于接收方的校验，工程上已经实现了，是正确的代码-rcrc16 anti-check codes for the receiver calibration, engineering has been achieved, is the correct code
Date : 2025-12-22 Size : 1kb User : 网报
[VHDL-FPGA-Verilog] clock DL : 0: 1.计时功能：包括时、分、秒的计时 2.定时与闹钟功能：能在设定的时间按发出闹铃声 3.校时功能：对小时、分钟和秒能手动调整以校准时间 4.整点报时功能 5.利用数码管显示时间-1. The timer function: including, minutes and seconds when the timing 2. The timing and alarm clock function: set time out according to the alarm 3. When the function of hours, minutes and: can manual adjustments to calibration second time 4. Strike on the function 5. Using digital pipe display time
Date : 2025-12-22 Size : 2kb User : 蒲公英
[VHDL-FPGA-Verilog] calibration DL : 0: CS5460校准程序，控制器为C8051F310，SPI通信协议，可以作为电表芯片示例-CS5460 calibration procedure, the controller for the C8051F310, SPI communication protocol, as the meter chip sample
Date : 2025-12-22 Size : 1kb User : yaokainan
[VHDL-FPGA-Verilog] module-Temperature DL : 0: DS18B20引脚功能 GND地，DQ数据总线，VDD电源电压 18B20共有三种形式的存储器资源，它们分别是： ROM 只读存储器，用于存放DS18B20ID编码，其前八位是单线系列编码，后面48位是芯片唯一的序列号，最后8位是以上56位的CRC码。DS18B20共64位ROM RAM 数据暂存器，数据掉电后丢失，共9个字节，每个字节8位，第1、2个字节是温度转换后的数据值信息，EEPROM 非易失性记忆体，用于存放长期需要保存的数据，上下限温度报警值和校验数据 -DS18B20 Function GND Ground pin, DQ data bus, VDD supply voltage 18B20 There are three forms of memory resources, they are: ROM read-only memory for storing DS18B20ID coding, the top eight single-family is encoded, followed by 48 is the chip serial number only, over the last eight is 56-bit CRC code. DS18B20 total of 64-bit ROM RAM data store, data loss after power-down, a total of 9 bytes, each byte 8-bit, 1, 2 bytes of temperature data converted value information, EEPROM non-volatile volatile memory for storage of long-term need to preserve data, upper and lower temperature alarm and calibration data
Date : 2025-12-22 Size : 9kb User : 袁亚楠
[VHDL-FPGA-Verilog] AD-converter-analog-simulation-- DL : 0: AD转换器的模拟信号仿真，写控制字, 再通过通信寄存器对设置寄存器、时钟寄存器进行访问。分别写控制字05H和40H、FFH,表示AD晶振2. 4576MHz, 更新频率60次/ s, 自校准模式, 差分输入。-AD converter analog simulation Write control word, again through the communication registers on Settings registers, clock registers visit. Write control words respectively in H and 40 H, FFH, said AD crystals 2. 4576 MHz, the frequency of updates 60 times/s, the calibration model, differential input.
Date : 2025-12-22 Size : 38kb User : 孟祥英
[VHDL-FPGA-Verilog] kt3tuo DL : 0: 基于FPGA的多功能数字钟系统（层次化设计）拓展功能包括：报时、校时校分、6到18点时段控制亮灯-Multi-functional digital clock system (hierarchical design) in the FPGA-based development features include: timekeeping, school Calibration of 6-18 hours to control lighting
Date : 2025-12-22 Size : 560kb User : cynthia
[VHDL-FPGA-Verilog] 17_parity DL : 0: 奇偶校验器，对八位二进制数据及其奇偶校验位的输入进行校验，输出正确的奇偶校验位。-Parity, eight binary data and its parity bit input calibration, and output the correct parity bit.
Date : 2025-12-22 Size : 2kb User : 叶杉
[VHDL-FPGA-Verilog] digital_freq DL : 0: 数字频率计，具有自动校验和测量两种功能，即能用标准时钟校验、测量精度。-Digital frequency meter, automatic calibration and measurement of two functions, that is, use the standard clock calibration, measurement accuracy.
Date : 2025-12-22 Size : 237kb User : 张龙
[VHDL-FPGA-Verilog] Digital-frequency-meter DL : 0: 具有测量和自动校验功能的十进制数字频率计。-Measurement and automatic calibration function decimal digital frequency meter.
Date : 2025-12-22 Size : 224kb User : 张三
[VHDL-FPGA-Verilog] clock-with-alarm-and-timer DL : 0: 黑金EP2C5QC808N系列，Quartus 11.0 中编译综合的数字钟，具有实时时钟运行，时钟校准，整点报时以及定时提醒功能，包含全部的工程文件。-Black EP2C5QC808N series, Quartus 11 compilation and synthesis of digital clock, with real-time clock operation, calibration of the clock, the whole point timekeeping, timing remind function, including all engineering documents.
Date : 2025-12-22 Size : 2.54mb User : 姜伟
[VHDL-FPGA-Verilog] VHDL DL : 0: 电路主要由七个模块组成：时钟产生模块用于产生1KHz的扫描时钟和1Hz的时钟；二分频模块用于对1Hz的时钟信号二分频；测量/校验选择模块用于功能选择；计数模块用于对输入的cp信号计数；送存选择、报警电路根据选择的量程送存信号并显示单位，在超出所选量程时报警；锁存器锁存要显示的结果；扫描显示模块在1KHz的扫描时钟下，依次扫描三个数码管，并显示结果。-The circuit consists of seven main modules: clock generation module is used to generate 1KHz scan clock and 1Hz clock frequency module for 1Hz clock signal frequency measurement/calibration selection module for function selection count module for the input the cp signal count deposit options, alarm deposit signal circuit according to the selected range and display units, within the selected range alarm latch latches to be displayed scanning display module at 1KHz the scan clock, scan the three digits, and displays the results.
Date : 2025-12-22 Size : 2kb User : 张骞
[VHDL-FPGA-Verilog] CALIBRATION DL : 0: Calibration is a comparison between measurements – one of known magnitude or correctness made or set with one device and another measurement made in as similar a way as possible with a second device. The device with the known or assigned correctness is called the standard. The second device is the unit under test, test instrument, or any of several other names for the device being calibrated.
Date : 2025-12-22 Size : 1kb User : GOPALAKRISHNAN E

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