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[VHDL-FPGA-Verilog] SRAM@DMA实验 DL : 0: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Date : 2026-01-10 Size : 33kb User : xf
[VHDL-FPGA-Verilog] SPI接口音频Codec实验 DL : 0: ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
Date : 2026-01-10 Size : 34kb User : xf
[VHDL-FPGA-Verilog] 一个8位CISC结构的精简CPU DL : 0: 一个8位CISC结构的精简CPU，2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler
Date : 2026-01-10 Size : 92kb User : 陈旭
[VHDL-FPGA-Verilog] mmcfpgaconfig.tar DL : 0: 基于FPGA的MMC卡实现，内部包含了C++仿真调试代码以及FPGA的实现代码，建立工程后可以之间编译调试-FPGA-based MMC card, Internal contains C++ Simulation debugging code, as well as the realization of FPGA code, the establishment of the project can be between the compiler debugging
Date : 2026-01-10 Size : 7kb User : 王弋妹
[VHDL-FPGA-Verilog] P8051 DL : 0: This a FREE tool chain which compiles C codes into 8051 binary code, converts the binary to RTL ROM, and simulate in Modelsim. SDCC is the compiler. Example compilation: cd compile sdcc --iram-size 0x80 --xram-size 0x800 t8051.c REM sdcc --iram-size 0x80 t8051.c packihx t8051.ihx > t8051.hex ..\test\mkrom.exe ..\compile\t8051.hex-This a FREE tool chain which compiles C codes into 8051 binary code, converts the binary to RTL ROM, and simulate in Modelsim.SDCC is the compiler.Example compilation: cd compile sdcc- iram-size 0x80- xram-size 0x800 t8051 . c REM sdcc- iram-size 0x80 t8051.c packihx t8051.ihx> t8051.hex .. estmkrom.exe .. compile 8051.hex
Date : 2026-01-10 Size : 7.73mb User : zhao xin ke
[VHDL-FPGA-Verilog] ctoverilog DL : 0: Verilog-to-C-Compiler: Simulator Generator
Date : 2026-01-10 Size : 300kb User : Abhishek
[VHDL-FPGA-Verilog] c16_latest.tar DL : 0: c16 ucore. this a 16 VHDL cpu core. complete with Assembler and C compiler. All src code included.-c16 ucore. this a 16 VHDL cpu core. complete with Assembler and C compiler. All src code included.
Date : 2026-01-10 Size : 1.63mb User : vtaranti
[VHDL-FPGA-Verilog] motor DL : 0: A C code for spinnig a small stepper motor in varriable velosities using codevision compiler.
Date : 2026-01-10 Size : 28kb User : Ali
[VHDL-FPGA-Verilog] Chapter-1 DL : 0: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Date : 2026-01-10 Size : 2kb User : shixiaodong
[VHDL-FPGA-Verilog] Chapter-2 DL : 0: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Date : 2026-01-10 Size : 5kb User : shixiaodong
[VHDL-FPGA-Verilog] Chapter-3 DL : 0: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Date : 2026-01-10 Size : 4kb User : shixiaodong
[VHDL-FPGA-Verilog] Chapter-4 DL : 0: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Date : 2026-01-10 Size : 7kb User : shixiaodong
[VHDL-FPGA-Verilog] Chapter-5 DL : 0: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Date : 2026-01-10 Size : 15kb User : shixiaodong
[VHDL-FPGA-Verilog] Chapter-6 DL : 0: 练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Date : 2026-01-10 Size : 3kb User : shixiaodong
[VHDL-FPGA-Verilog] Chapter-7 DL : 0: 练习七在verilog hdl中使用任务（task）319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Date : 2026-01-10 Size : 7kb User : shixiaodong
[VHDL-FPGA-Verilog] Chapter-8 DL : 0: 练习八利用有限状态机进行时序逻辑的设计322 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Date : 2026-01-10 Size : 328kb User : shixiaodong
[VHDL-FPGA-Verilog] modelsim-C_compiler_issue DL : 0: modelsim的C compiler问题，请需要者下载参考-modelsim the C compiler problem, for those who need to download reference
Date : 2026-01-10 Size : 175kb User : 磊