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[VHDL-FPGA-Verilog] i2c总线的vhdl实现和vxworks的文件系统 DL : 1: i2c总线的vhdl实现和vxworks的文件系统-i2c bus VHDL realization and VxWorks file system
Date : 2025-12-29 Size : 16kb User :
[VHDL-FPGA-Verilog] adma.tar DL : 0: 基于AMBA规范的总线VERILOG HDL 源代码-Based on the AMBA bus specification VERILOG HDL source code
Date : 2025-12-29 Size : 12kb User : maliang
[VHDL-FPGA-Verilog] lctl_1.2 DL : 0: CPLD的例子程序1,EPM7128芯片,ISA总线-Examples of CPLD procedures 1, EPM7128 chip, ISA Bus
Date : 2025-12-29 Size : 212kb User : Sean Cheung
[VHDL-FPGA-Verilog] spi DL : 0: SPI总线，VHDL语言，硬件描述语言源码-SPI bus, VHDL language, hardware description language source code
Date : 2025-12-29 Size : 3kb User : 郑文棋
[VHDL-FPGA-Verilog] I2C_CANBUS_USB_fpga DL : 0: CAN总线，Ｉ２Ｃ，ＵＳＢ等的ＦＰＧＡ实现源码-CAN bus, I2C, USB, etc. FPGA to achieve source
Date : 2025-12-29 Size : 1.44mb User : 宁新
[VHDL-FPGA-Verilog] i2c_altera DL : 0: I2C总线控制器 altera公司提供VHDL实现代码-I2C bus controller altera companies realize VHDL code
Date : 2025-12-29 Size : 1.52mb User : 张庆顺
[VHDL-FPGA-Verilog] can_IPCORE DL : 0: CAN总线IPCORE，采用Verilog HDL语言实现。-CAN bus IPCORE, using Verilog HDL language.
Date : 2025-12-29 Size : 60kb User : feifei
[VHDL-FPGA-Verilog] vspi DL : 0: spi总线控制器，包含vhdl和verilog两种代码方式来实现。-spi bus controller, including VHDL and Verilog code in two ways to achieve.
Date : 2025-12-29 Size : 13kb User : wangdong
[VHDL-FPGA-Verilog] SPIBusVerilog DL : 0: SPI串行总线接口的Verilog实现，详细讲解实现过程。-SPI serial bus interface Verilog realization elaborate on the realization of the process.
Date : 2025-12-29 Size : 389kb User : zhlm88
[VHDL-FPGA-Verilog] CAN_Bus_basis DL : 1: 基于CAN总线的汽车仿真。汽车实例为大众途安。分辨率为1024x768。-Based on the CAN bus automotive simulation. Automotive examples for the public Touran. A resolution of 1024x768.
Date : 2025-12-29 Size : 224kb User : 张宇
[VHDL-FPGA-Verilog] wishbone_VHDL DL : 0: wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快成为ip通信的主流-Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
Date : 2025-12-29 Size : 454kb User : 王鹏
[VHDL-FPGA-Verilog] 68K_ebiu DL : 0: It contains a vhdl description of the external bus interface unit for 68000 processor. currently only read and write cycle are supported
Date : 2025-12-29 Size : 3kb User : Pankaj
[VHDL-FPGA-Verilog] bus DL : 0: 显示总线扩展的_VHDL代码，大家共同学习。-Show that the expansion bus _VHDL code, a common study.
Date : 2025-12-29 Size : 188kb User : 肖
[VHDL-FPGA-Verilog] CAN_IP DL : 1: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Date : 2025-12-29 Size : 60kb User : 普林斯
[VHDL-FPGA-Verilog] canbus DL : 1: CAN通信协议的硬件描述语言代码，用于FPGA的总线接口控制器开发-CAN communication protocol of the hardware description language code for the FPGA bus interface controller development
Date : 2025-12-29 Size : 842kb User : shigengxin
[VHDL-FPGA-Verilog] SDCard_Controller DL : 0: SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口，方便与其他IP连接使用。 -SD Card Controller IP. Compatible with SD Card Agreement 2.0. With the wishbone bus interface to facilitate the use of other IP connections.
Date : 2025-12-29 Size : 24kb User : xiafei
[VHDL-FPGA-Verilog] CODE DL : 0: AHB总线下的slave ram的verilog代码-AHB bus slave ram verilog
Date : 2025-12-29 Size : 1kb User : 龙的传人
[VHDL-FPGA-Verilog] clkx_bus DL : 0: Imprtant example clk bus for VHDL
Date : 2025-12-29 Size : 3kb User : Haitham
[VHDL-FPGA-Verilog] bus DL : 0: 一个简单的总线bus代码，初学者可以借鉴学习-A simple bus-bus code, beginners can learn to learn
Date : 2025-12-29 Size : 1kb User : tom
[VHDL-FPGA-Verilog] bus DL : 0: 公交车系统基于FPGA芯片的基础上，增加了数码管显示模块、语音自动报站模块、红外通信模块。站牌系统采用以FPGA为核心的主控芯片，增加液晶显示模块、红外通信模块、RS232总线模块、指示灯显示模块等。(The bus system is based on FPGA chip. It adds digital tube display module, voice automatic reporting module and infrared communication module. The bus stop system adopts FPGA as the core of the main control chip, add LCD module, infrared communication module, RS232 bus module, indicator light display module and so on.)
Date : 2025-12-29 Size : 6.4mb User : 幽山之隅

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