Search - bit c - CodeBus

Search - bit c - List

[VHDL-FPGA-Verilog] alu_16 DL : 1: 三种16位整数运算器的ALU设计方法，调用库函数74181（4位ALU），组成串行16位运算器。(用74181的正逻辑) B．调用库函数74181和74182，组成提前进位16位运算器。(用74181的正逻辑) 注意：调74181库设计，加进位是“0”有效，减借位是“1”有效，所以最高位进位或借位标志寄存器要统一调整到高有效 C．用always @，case方式描述16位运算器。-Three 16-bit integer arithmetic logic unit of the ALU design methodology, called library function 74181 (4 ALU), composed of serial 16-bit arithmetic logic unit. (With 74,181 positive logic) B. Call library functions 74181 and 74182 to form the advance into the 16-bit arithmetic logic unit. (With 74,181 positive logic) Note: 74,181 Treasury tune the design, add bit is
Date : 2026-01-03 Size : 1kb User : yifang
[VHDL-FPGA-Verilog] 16bitCLA DL : 0: 基于Verilog HDL的16位超前进位加法器分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
Date : 2026-01-03 Size : 7kb User : 韩伟
[VHDL-FPGA-Verilog] cfq8 DL : 0: VHDL语言编写8位乘法器非常实用语言绝对正确经过仿真的-VHDL language is very practical 8-bit multiplier is absolutely correct language after simulation
Date : 2026-01-03 Size : 7kb User : 网保
[VHDL-FPGA-Verilog] Multiplier DL : 0: 4 bit multiplier written in behavioral VHDL, using logic gate logic. inputs are A and B (4 bit each) and output is C (8 bits).
Date : 2026-01-03 Size : 1kb User : avi
[VHDL-FPGA-Verilog] 8bit_RISC_CPU_RTL_Code DL : 0: 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
Date : 2026-01-03 Size : 78kb User : 曾亮
[VHDL-FPGA-Verilog] fpgaConfig_V1_2_SFLASH_20090507a DL : 0: 自己写的一个使用单片机配置FPGA的下位机C代码，使用一个C8051F330,外置SPI FLASH,通过串口可将程序写入FLASH,上电时自动加载到FPGA完成配置。-Wrote it myself, using a microcontroller to configure FPGA code for the next bit plane C, using a C8051F330, external SPI FLASH, the program is written through the serial port can be FLASH, power-on automatically loaded into the FPGA to complete the configuration.
Date : 2026-01-03 Size : 2.28mb User : 胡小平
[VHDL-FPGA-Verilog] multiplier-accumulator(vhdl) DL : 0: 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of multiplicand X and 4-bit multiplier Y input, the temporary 4-bit registers in the register A and B, registers A and B multiplied by the output of the first, to be 8-bit product, the product further with the 8-bit output of register C, the sum of, the sum of the results stored in register C,. The output register C is also the system output Z. (Original, which are multiply and accumulate some part may be raised separately, very good use)
Date : 2026-01-03 Size : 945kb User : jlz
[VHDL-FPGA-Verilog] Priority_Encoder DL : 0: Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded output. Then, it is a multi-input data line, combinational logic circuit that converts the logic level "1" data at its inputs to an equivalent binary code at its output. Generally encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon the number of data input lines and a "n-bit" encoder has 2n input lines with common types that include 4-to-2, 8-to-3 and 16-to-4 line configurations. Encoders are available to encode either a decimal or hexadecimal input pattern to typically a binary or B.C.D. output code.-Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded output. Then, it is a multi-input data line, combinational logic circuit that converts the logic level "1" data at its inputs to an equivalent binary code at its output. Generally encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon the number of data input lines and a "n-bit" encoder has 2n input lines with common types that include 4-to-2, 8-to-3 and 16-to-4 line configurations. Encoders are available to encode either a decimal or hexadecimal input pattern to typically a binary or B.C.D. output code.
Date : 2026-01-03 Size : 13kb User : VLSI
[VHDL-FPGA-Verilog] Encoder_Using_Assign_Statement DL : 0: Encoder Using Assign Statements: Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded output. Then, it is a multi-input data line, combinational logic circuit that converts the logic level "1" data at its inputs to an equivalent binary code at its output. Generally encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon the number of data input lines and a "n-bit" encoder has 2n input lines with common types that include 4-to-2, 8-to-3 and 16-to-4 line configurations. Encoders are available to encode either a decimal or hexadecimal input pattern to typically a binary or B.C.D. output code.
Date : 2026-01-03 Size : 10kb User : VLSI
[VHDL-FPGA-Verilog] 4v2 DL : 0: ENTITY maj IS PORT(a,b,c : IN BIT m : OUT BIT) END maj --Dataflow style architecture --Behavioural style architecture using a look-up table ARCHITECTURE using_table OF maj IS BEGIN PROCESS(a,b,c) CONSTANT lookuptable : BIT_VECTOR(0 TO 7) := "00010111" VARIABLE index : NATURAL BEGIN index := 0 --index must be cleared each time process executes IF a = 1 THEN index := index + 1 END IF IF b = 1 THEN index := index + 2 END IF IF c = 1 THEN index := index + 4 END IF m <= lookuptable(index) END PROCESS END using_table ------------------3,5,6,7 is 1 so 110 101 011 111 is 1-ENTITY maj IS PORT(a,b,c : IN BIT m : OUT BIT) END maj --Dataflow style architecture --Behavioural style architecture using a look-up table ARCHITECTURE using_table OF maj IS BEGIN PROCESS(a,b,c) CONSTANT lookuptable : BIT_VECTOR(0 TO 7) := "00010111" VARIABLE index : NATURAL BEGIN index := 0 --index must be cleared each time process executes IF a = 1 THEN index := index+ 1 END IF IF b = 1 THEN index := index+ 2 END IF IF c = 1 THEN index := index+ 4 END IF m <= lookuptable(index) END PROCESS END using_table ------------------3,5,6,7 is 1 so 110 101 011 111 is 1
Date : 2026-01-03 Size : 134kb User : 赵中原
[VHDL-FPGA-Verilog] ofdmbaseband DL : 0: the OFDM PHY is adaptive therefore it supports multiple schemes BPSK, QPSK, 16-QAM and 64-QAM for data carriers’ modulation. The constellation diagrams are gray mapped and shows the magnitudes I and Q (In-phase and Quadrature) components of each incoming bit(s) combination along with their normalization factor C to calculate magnitude of each model
Date : 2026-01-03 Size : 1.43mb User : san
[VHDL-FPGA-Verilog] ass1_2_hamming DL : 0: Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a Verilog module that will generate a 7-bit encoded data from a 4-bit data. Simulate your design for two inputs. Use even or odd parity according to the least significant figure of your ID number. b) Develop a Veriog module for generating pseudorandom 4-bit data using Linear Feedback Shift Register( LFSR) method. c) Develop a Verilog module to emulate one bit error in the data transmission. This can be done by changing only one of the encoded bits at each clock cycle. You may use a ring-counter and XOr gates for doing this. This arrangement will insert error in consecutive bits at each clock cycle. d) Design a Hamming error detection and correction circuit to restore the original data. e) Compare the original data with the restored data to verify the error correction capability of your design. If the two data sets are equal an OK signal will be set.
Date : 2026-01-03 Size : 1.08mb User : wei chenghao
[VHDL-FPGA-Verilog] jianyishuzipinlvji DL : 0: （1）基本要求： a．被测信号的频率范围为1～20kHz，用4位数码管显示数据。 b．测量结果直接用十进制数值显示。 c．被测信号可以是正弦波、三角波、方波，幅值1～3V不等。 d．具有超量程警告（可以用LED灯显示，也可以用蜂鸣器报警）。 e．当测量脉冲信号时，能显示其占空比（精度误差不大于1 ）。（2）发挥部分 a．修改设计，实现自动切换量程。 b．构思方案，使整形时，以实现扩宽被测信号的幅值范围 -(1) Basic requirements: a. Frequency range of the signal 1 ~ 20kHz, with a 4-bit digital display data. b. Measurement results show the direct use of the decimal value. c. The measured signal can be sine wave, triangle wave, square wave, amplitude 1 ~ 3V range. d. Super-range warning (you can use LED lights display, you can also use the buzzer alarm.) e. When measuring the pulse signal, to show its duty cycle (precision error is less than 1 ). (2) to play a part of a. Modify the design, automatic switching range. b. The idea of the program, so that when the plastic in order to achieve broaden the scope of the measured signal amplitude
Date : 2026-01-03 Size : 4kb User : longking
[VHDL-FPGA-Verilog] fpgaconvert DL : 1: 将xilinx 的fpga配置bit文件转换为c语言文件，通过cpu配置fpga-translate？i can t
Date : 2026-01-03 Size : 2kb User : 王凯
[VHDL-FPGA-Verilog] Jpeg_decoder DL : 1: It is jpeg_decoder program. Source code are C and Verilog HDL.File .c reads data from jpeg and convert it to binary bit stream.Decoder is by verilog file
Date : 2026-01-03 Size : 195kb User : doulce
[VHDL-FPGA-Verilog] alu-10-10 DL : 0: 16位运算器，包含+、-、与或非、移位等功能，内部指定a、b、cin，输入clk与rst，输出16位y与c\z标志位-16-bit arithmetic unit, including+,-, and or, shift and other functions, within the specified a, b, cin, input clk and rst, 16-bit output y and c \ z flag
Date : 2026-01-03 Size : 2kb User : 张海洋
[VHDL-FPGA-Verilog] berlekamp_parallel DL : 0: The Berlekamp multiplier [3] uses two basis representations, the polynomial basis for the multiplier and the dual basis for the multiplicand and the product. Because it is normal practice to input all data in the same basis, this means some basis transformation circuits will be required. Fortunately for m = (3, 4, 5, 6, 7, 9, 10) the basis conversion from the dual to the polynomial basis - and vice versa - is merely a reordering of the basis coefficients [38]. For the important case m = 8 - for example the error-correcting systems used in CDs, DAT and many other applications operate over GF(28) - this basis conversion requires a reordering and two additions of the basis coefficients (Appendix C). In practice therefore, two additional XOR gates are required. Even including the extra hardware for basis conversions, the Berlekamp multiplier is known to have the lowest hardware requirements of all available bit-serial multipliers [24].
Date : 2026-01-03 Size : 153kb User : guctiida
[VHDL-FPGA-Verilog] password DL : 0: verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。-verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.
Date : 2026-01-03 Size : 565kb User : 陈振睿
[VHDL-FPGA-Verilog] CRC.C DL : 0: 下面以最常用的CRC-16为例来说明其生成过程。　　CRC-16码由两个字节构成，在开始时CRC寄存器的每一位都预置为1，然后把CRC寄存器与8-bit的数据进行异或(异或：二进制运算相同为0，不同为1；0^0=0 0^1=1 1^0=1 1^1=0)，　　之后对CRC寄存器从高到低进行移位，在最高位（MSB）的位置补零，而最低位（LSB，移位后已经被移出CRC寄存器）如果为1，则把寄存器与预定义的多项式码进行异或，否则如果LSB为零，则无需进行异或。重复上述的由高至低的移位8次，第一个8-bit数据处理完毕，用此时CRC寄存器的值与下一个8-bit数据异或并进行如前一个数据似的8次移位。所有的字符处理完成后CRC寄存器内的值即为最终的CRC值。 -Below the most commonly used CRC-16 as an example to illustrate the generation process. CRC-16 yards by two-bytes at the beginning of every one of the CRC register is preset to 1, then the CRC register with the 8-bit data XOR (exclusive or: the same as the binary operation 0, different 1 0 ^ 0 = 0 0 ^ 1 = 1 1 ^ 0 = 1 1 ^ 1 = 0), After the shift the CRC register from highest to lowest, the most significant bit (MSB) position zeros, the least significant bit (LSB after the shift has been out of the CRC register) 1, put the register with pre-defined item code different, or, otherwise, if the LSB is zero, you do not need to XOR. Repeat the above the descending order of the shift eight times, the first 8-bit data processing is completed, such as previous data like 8 times shift the CRC register values and the next 8-bit data XOR and . After completion of all the characters deal with the value of the CRC register is the final CRC value.
Date : 2026-01-03 Size : 11kb User : malimin
[VHDL-FPGA-Verilog] 5.c DL : 0: ; for 16-bit app support [386Enh] woafont=dosapp.fon EGA80WOA.FON=EGA80WOA.FON EGA40WOA.FON=EGA40WOA.FON CGA80WOA.FON=CGA80WOA.FON CGA40WOA.FON=CGA40WOA.FON
Date : 2026-01-03 Size : 2kb User : fov120

« 12 »