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[VHDL-FPGA-Verilog] SPI接口音频Codec实验 DL : 0: ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
Date : 2025-12-27 Size : 34kb User : xf
[VHDL-FPGA-Verilog] I2S DL : 0: 这是一个I2S接口的VHDL实现源代码，I2S是一个通用的音频接口。-This is a I2S interface VHDL source code, I2S is a generic audio interface.
Date : 2025-12-27 Size : 1.51mb User : 孙浩
[VHDL-FPGA-Verilog] DE2_SD_Card_Audio DL : 0: SD卡读取音频数据，由VGA显示。Verilog HDL语言编写，适用DE2实验箱-SD card reader audio data from the VGA display. Verilog HDL language, the application of the experimental box DE2
Date : 2025-12-27 Size : 3kb User : 白雪
[VHDL-FPGA-Verilog] DE2_WEB DL : 1: 用DE2板子实现的音频分析器,需要安装quartus2,硬件需要DE2的板子-DE2 board using the Audio Analyzer realize the need to install quartus2, the hardware needs of the DE2 board
Date : 2025-12-27 Size : 8.23mb User : 任迎
[VHDL-FPGA-Verilog] S12_AudioLoopback_DAV_MIC DL : 0: 从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code
Date : 2025-12-27 Size : 2.3mb User : zl.yin
[VHDL-FPGA-Verilog] yinpinxinhaofenxiyi DL : 0: 基于vhdl的音频信号分析仪，获电子设计大赛一等奖-VHDL-based audio signal analyzer, an electronic design competition first prize
Date : 2025-12-27 Size : 4.94mb User : 杨天
[VHDL-FPGA-Verilog] test81 DL : 0: DE2 音频处理从SD卡读去音乐数据在做相应的处理，通过音频输出口播放同事可以从音频输入口加入相应的音乐也可以从MIK口输入音频-DE2 audio processing time from the SD card to do the music data in the processing, I play through the audio output from the audio input of my colleagues to join the music I can also input audio from the mouth MIK
Date : 2025-12-27 Size : 4.89mb User : lin jin
[VHDL-FPGA-Verilog] altera_mf DL : 0: 高清或标清SDI信号，通过编写的FPGA的Audio程序进行处理。-HD or SD SDI signals, through the development of the FPGA-Audio procedures.
Date : 2025-12-27 Size : 9kb User : 邢占鹏
[VHDL-FPGA-Verilog] DecoderAudio DL : 1: 本程序为SDI的音视频分离Verilog程序，信号通过分离后，可以分离出视频和音频信号。-This procedure for the separation of SDI audio and video Verilog program, the signal after the separation, can be isolated video and audio signals.
Date : 2025-12-27 Size : 2kb User : 邢占鹏
[VHDL-FPGA-Verilog] MAC_MP3_Hardware DL : 0: MPeg audio encoder/decoder codes
Date : 2025-12-27 Size : 4.32mb User : prass
[VHDL-FPGA-Verilog] Audio_Bit_Counter DL : 0: The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Date : 2025-12-27 Size : 1kb User : gasha
[VHDL-FPGA-Verilog] Audio_Out_Serializer DL : 0: The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Date : 2025-12-27 Size : 1kb User : gasha
[VHDL-FPGA-Verilog] Avalon_Audio DL : 0: The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Date : 2025-12-27 Size : 2kb User : gasha
[VHDL-FPGA-Verilog] Clock_Edge DL : 0: The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Date : 2025-12-27 Size : 1kb User : gasha
[VHDL-FPGA-Verilog] DE2_i2sound DL : 0: 基于FPGA的音频信号A/D转换，适用于DE2开发板。-FPGA-based audio signal A/D conversion, for DE2 development board.
Date : 2025-12-27 Size : 34kb User : wendy
[VHDL-FPGA-Verilog] audio_bargraph DL : 0: Allows to display an audio bargraph (peak meter and vu meter) of a HD-SD SDI embedded audio signal .
Date : 2025-12-27 Size : 29kb User : Jacques
[VHDL-FPGA-Verilog] DE2_70_AUDIO DL : 0: 是用VERILOG HDL和NIOS II C/C++ 编的DE2-70板子的音频编解码芯片的使用工程-Is VERILOG HDL and NIOS II C/C++ code of the DE2-70 board in the audio codec chip, the use of project
Date : 2025-12-27 Size : 20.57mb User : 覃建策
[VHDL-FPGA-Verilog] TERASIC_AUDIO DL : 0: 友晶提供的Audio的IP核。这个IP核提供了Verilog的硬件部分源码和相应的HAL驱动程序。-Audio provided by Friends of Crystal' s IP core. The IP core provides a Verilog hardware part of the source and the corresponding HAL driver.
Date : 2025-12-27 Size : 123kb User : changjiang
[VHDL-FPGA-Verilog] Wolfson-WM8731-audio-CODEC DL : 0: audio codec data sheet
Date : 2025-12-27 Size : 664kb User : Venky
[VHDL-FPGA-Verilog] DE2-platform-hardware-audio-playback DL : 0: 在FPGA-DE2平台上的纯硬件录音播放实验-Purely on the DE2 platform hardware audio playback experiment
Date : 2025-12-27 Size : 1.1mb User : rjy

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