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[VHDL-FPGA-Verilog] XAPP211 DL : 0: Xilinx APP Generators Using the SRL Macro
Date : 2026-01-09 Size : 70kb User : ryan
[VHDL-FPGA-Verilog] Oreilly.Programming.Google.App.Engine.Nov.2009.ra DL : 0: E-book: Oreilly.Programming.Google.App.Engine.Nov.2009
Date : 2026-01-09 Size : 3.01mb User : hank8617
[VHDL-FPGA-Verilog] FIFO-APP-IN-ASIC DL : 0: FIFO在ASIC中的设计应用，用于图像滤波处理，解决了ASIC中图像处理过程中数据缓存的需求，有一定实用价值-FIFO in the ASIC Design and application for image filtering, image processing ASIC to resolve the data caching process needs a certain practical value
Date : 2026-01-09 Size : 254kb User : tutu
[VHDL-FPGA-Verilog] 3rd-First-App DL : 0: MSTAR平台上的第一个3RD应用程序，对于MSTAR平台刚入门，并且不知道如何编写第三方应用程序的开发者很有帮助。这是一个3RD程序的基本的框架-MSTAR platform, the first 3RD application platform for the MSTAR has just started, and do not know how to write third-party applications developers helpful. This is a basic program framework 3RD
Date : 2026-01-09 Size : 35kb User : shellex
[VHDL-FPGA-Verilog] (www.entrance-exam.net)-GEN.-APP DL : 0: verilog hdl code for speed control of dc motor
Date : 2026-01-09 Size : 397kb User : syed rafeh hussaini
[VHDL-FPGA-Verilog] edk DL : 0: edk is useful document for interfacing of various a-edk is useful document for interfacing of various app
Date : 2026-01-09 Size : 10kb User : sai
[VHDL-FPGA-Verilog] xapp423 DL : 0: xilinx的xapp423，关于pace进行约束IO管脚的应用案例，艰难找到的-xilinx s app. about Creating Pin-Out Prior to Implementation with PACE, hard to find out
Date : 2026-01-09 Size : 83kb User : russellwong
[VHDL-FPGA-Verilog] r7lite DL : 0: R7Lite是基于Xilinx的Kintex7系列FPGA的PCI Express参考设计代码，PCIe 2.0 4x模式，包括了FPGA实现，Linux下驱动和测试例程。-R7Lite is a PCIe Reference design based on Xilinx Kintex7 FPGA,including FPGA code ,Linux Driver and Testing App
Date : 2026-01-09 Size : 20.67mb User : yao
[VHDL-FPGA-Verilog] Spartan-6-PCIE_tutorial2 DL : 0: xilinx spartan 6 pcie 仿真教程，v2.4版本，主要是讲解如何使用pcie core和自己的用户逻辑级联仿真。-xilinx spartan 6 pcie sim tutorial ，tell readers how to sim using pcie core and user app logic,tool:questasim
Date : 2026-01-09 Size : 844kb User : liuluren
[VHDL-FPGA-Verilog] AS-SSD-Benchmark DL : 0: this APP likes shit do you like you can eatand happy go fucking it -this APP likes shit do you like you can eatand happy go fucking it
Date : 2026-01-09 Size : 258kb User : bluesffa
[VHDL-FPGA-Verilog] USB_SoftLock DL : 0: USB SoftLock, 包含VHDL for Xilinx FPGA，上位机驱动以及应用程序-USB SoftLock, Include VHDL for Xilinx FPGA, PC Driver and App
Date : 2026-01-09 Size : 157kb User : Eddie
[VHDL-FPGA-Verilog] 5.c DL : 0: ; for 16-bit app support [386Enh] woafont=dosapp.fon EGA80WOA.FON=EGA80WOA.FON EGA40WOA.FON=EGA40WOA.FON CGA80WOA.FON=CGA80WOA.FON CGA40WOA.FON=CGA40WOA.FON
Date : 2026-01-09 Size : 2kb User : fov120
[VHDL-FPGA-Verilog] LwIP_raw_apps_sdk DL : 0: Vivado sdk raw mode app to implement LwIP
Date : 2026-01-09 Size : 2.29mb User : bk2000
[VHDL-FPGA-Verilog] LwIP_socket_apps_sdk DL : 0: Vivado sdk socket mode app to implement LwIP
Date : 2026-01-09 Size : 2.07mb User : bk2000
[VHDL-FPGA-Verilog] Viscosity_1.7.7[sn] DL : 0: Viscosicty is a vpn app
Date : 2026-01-09 Size : 15.71mb User : vartana