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[VHDL-FPGA-Verilog] jiaotd DL : 0: AD0809的源程序，能使EDA工具箱显示AD0809，具备树模转换功能-AD0809 a source, EDA can show AD0809 a toolbox, with tree-analog converter function
Date : 2026-01-18 Size : 1kb User : 安陪应
[VHDL-FPGA-Verilog] jiaotongdeng DL : 0: 一个用VHDL编写的在CPLD上实现模拟交通灯的程序源代码-a VHDL prepared by the CPLD on the analog signal source code
Date : 2026-01-18 Size : 385kb User : 田冰
[VHDL-FPGA-Verilog] DE2_TV DL : 0: 一个模拟视频输入转VGA视频输出的Verilog程序，视频解码芯片采用ADV7181B，VGA DAC采用ADV7123，强力推荐-an analog video input to VGA video output Verilog procedures, Video decoder chip used ADV7181B, VGA DAC used ADV7123, strongly recommended!
Date : 2026-01-18 Size : 26kb User : 李全
[VHDL-FPGA-Verilog] dds_fpga DL : 0: DDS在现在运用月来越广泛，在相对带宽、频率转换时间、相位连续性、正交输出、高分辨力以及集成化等方面都远远超过了传统频率合成技术所能达到的水平，为系统提供了优于模拟信号源的性能。利用DDS技术可以很方便地实现多种信号。在FPGA上实现的DDS-DDS now to the use of more extensive relative bandwidth, frequency conversion time, phase continuity, quadrature output, high-resolution and integration, and other aspects far more than the traditional frequency synthesizer technology can achieve the level To provide a superior analog signal source performance. DDS technology can be used very easily to a variety of signal. FPGA Implementation of DDS
Date : 2026-01-18 Size : 176kb User : 孙洪亮
[VHDL-FPGA-Verilog] ADCINT DL : 0: 此程序基于ADC0809,它是CMOS的8位A/D转换器，片内有8路模拟开关，可控制8个模拟量中的一个进入转换器中。-Connection between ADC 0809, it was the eight CMOS A/D converters. Tablets containing eight analog switches, control eight of analog converters enter a Chinese.
Date : 2026-01-18 Size : 1kb User : 空气
[VHDL-FPGA-Verilog] VHDL_adc0809 DL : 0: 驱动模数转换器ADC0809转换的VHDL代码-Driver Analog to Digital Conversion Connection between ADC 0809 VHDL code
Date : 2026-01-18 Size : 106kb User : YI
[VHDL-FPGA-Verilog] ADC_16bit DL : 0: 用verilog硬件描述语言编写的16位数模转换器的源代码，可以综合-with verilog hardware description language of 16 Digital to Analog source code can be integrated
Date : 2026-01-18 Size : 1kb User : awp
[VHDL-FPGA-Verilog] adc DL : 0: Analog-to-Digital Converter，VHDL code-Analog-to-Digital Converter, VHDL code
Date : 2026-01-18 Size : 14kb User : leigh lee
[VHDL-FPGA-Verilog] S3E_AnalogIO DL : 0: it is a analog i/o interface written in verilog .it will work on spartan 3 xilini devices.
Date : 2026-01-18 Size : 2kb User : ali
[VHDL-FPGA-Verilog] pll DL : 0: 模拟锁相环（apll）的一些simulink模型-Analog phase-locked loop (apll) some simulink model
Date : 2026-01-18 Size : 717kb User : prescaler
[VHDL-FPGA-Verilog] dac DL : 0: Digital to Analog Converter code VHDL
Date : 2026-01-18 Size : 3kb User : gfngk
[VHDL-FPGA-Verilog] Foundations-of-Analog-and-Digital-Circuit-Design. DL : 0: Foundations of Analog and Digital Circuit Design
Date : 2026-01-18 Size : 7.2mb User : mucko
[VHDL-FPGA-Verilog] Analog-to-digital-converter DL : 0: 模数转化器，64位双精度的模拟输入值，16位数字输出-Analog to digital converter, 64-bit double-precision analog inputs, 16 digital outputs
Date : 2026-01-18 Size : 1kb User : chenxuying
[VHDL-FPGA-Verilog] Analog-Circuits--4Ed(Tongshibai) DL : 0: 模拟电子技术基础第四版，带课件和习题答案，童诗白著，带书签-Analog Circuits 4th Edition
Date : 2026-01-18 Size : 50.64mb User : liyuyao
[VHDL-FPGA-Verilog] Analog-Circuits--3Ed(Tongshibai) DL : 0: 模拟电子技术基础第三版，童诗白著，带书签-Analog Circuits, 3rd Edition
Date : 2026-01-18 Size : 10.94mb User : liyuyao
[VHDL-FPGA-Verilog] Analog-Circuit-4Ed-Exercise-Answer- DL : 0: 模拟电子技术基础课后练习题答案，童诗白第四版-Analog Circuit 4Ed Exercise Answer
Date : 2026-01-18 Size : 867kb User : liyuyao
[VHDL-FPGA-Verilog] analog-behavioral-modeling-with-the-verilog-a-lan DL : 0: analog behavioral modeling using Verilog-AMS
Date : 2026-01-18 Size : 7.55mb User : choi,kwangho
[VHDL-FPGA-Verilog] AD-converter-analog-simulation-- DL : 0: AD转换器的模拟信号仿真，写控制字, 再通过通信寄存器对设置寄存器、时钟寄存器进行访问。分别写控制字05H和40H、FFH,表示AD晶振2. 4576MHz, 更新频率60次/ s, 自校准模式, 差分输入。-AD converter analog simulation Write control word, again through the communication registers on Settings registers, clock registers visit. Write control words respectively in H and 40 H, FFH, said AD crystals 2. 4576 MHz, the frequency of updates 60 times/s, the calibration model, differential input.
Date : 2026-01-18 Size : 38kb User : 孟祥英
[VHDL-FPGA-Verilog] Analog-to-Digital-Converter-Model DL : 0: Analog-to-Digital Converter Model.
Date : 2026-01-18 Size : 2kb User : jerryzhang
[VHDL-FPGA-Verilog] AD_TLC549-analog-signal-acquisition DL : 0: AD_TLC549采集模拟信号AD_TLC549 analog signal acquisition AD_TLC549 analog signal acquisition-AD_TLC549 analog signal acquisitionAD_TLC549 analog signal acquisitionAD_TLC549 analog signal acquisition
Date : 2026-01-18 Size : 1.76mb User : 李雅哲

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