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[VHDL-FPGA-Verilog] 多功能电子钟 DL : 0: 具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.
Date : 2025-12-25 Size : 6kb User : 张建
[VHDL-FPGA-Verilog] Verilog DHL数字钟 DL : 0: 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
Date : 2025-12-25 Size : 2kb User : 谢树扬
[VHDL-FPGA-Verilog] clock DL : 0: 用VHDL语言编写的一个闹钟程序，可以整点报时，设置时间，设置闹钟。-VHDL language using an alarm clock to prepare procedures, can be the whole point of time, set time, set an alarm clock.
Date : 2025-12-25 Size : 750kb User : zhg
[VHDL-FPGA-Verilog] clock DL : 0: 数字钟的VHDL源程序，可实现整点报时、闹钟的功能，还有常有星期的显示，已调试过-Digital Clock in VHDL source code, enabling the whole point timekeeping, alarm clock function, there are often weeks of shows that have been debug
Date : 2025-12-25 Size : 1.28mb User : 玉峰
[VHDL-FPGA-Verilog] CLOCK DL : 0: 可以调整时间和设置闹钟的数字钟(VHDL)-Can adjust the time and set the digital clock alarm clock (VHDL)
Date : 2025-12-25 Size : 885kb User : iyoung
[VHDL-FPGA-Verilog] clock DL : 0: 数字钟的程序，功能说明如下所示： 1.完成秒／分／时的依次显示并正确计数； 2.秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位； 3.定时闹钟：实现整点报时，通过语音设备来实现具体的报时； 4.时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整 5.可以选择使用12进制计时或者24进制计时。使用QuartusII6.0编译仿真通过，语言使用的是VHDL，可以方便的移植到其他的平台上面。 -Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.
Date : 2025-12-25 Size : 227kb User : 余宾客
[VHDL-FPGA-Verilog] clock DL : 0: 两个按键控制校时的VHDL时钟源码，带定时闹钟和日历功能-Two buttons control the school at the time of VHDL source clock, alarm clock and calendar with timing function
Date : 2025-12-25 Size : 2kb User : liu
[VHDL-FPGA-Verilog] multifunction_clock DL : 0: 此为多功能数字电子钟的vhdl代码，有闹钟、时间可调、计时等功能-This is a multi-function digital electronic clock VHDL code, has an alarm clock, time adjustable, timing and other functions
Date : 2025-12-25 Size : 4kb User : naturexu
[VHDL-FPGA-Verilog] shuzizhong DL : 0: 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
Date : 2025-12-25 Size : 416kb User : 盼盼
[VHDL-FPGA-Verilog] clock DL : 0: 可以实现时间调节，十二，二十四小时转换，定时，闹钟的时钟-Can be time-conditioning, 12, 24 hours conversion, time, alarm clock
Date : 2025-12-25 Size : 407kb User : 王明
[VHDL-FPGA-Verilog] alarm-clock DL : 0: 基于vhdl的数字闹钟的设计。可实现计时、闹钟、调节时间功能。可以在FPGA上实现。-VHDL-based digital alarm clock design. Can achieve a time, alarm clock, adjust time function. FPGA implementation can be on.
Date : 2025-12-25 Size : 2kb User : tony
[VHDL-FPGA-Verilog] clock DL : 0: VHDL数字闹钟实现，运用八位LED显示-VHDL realization of the digital alarm clock, the use of eight LED display
Date : 2025-12-25 Size : 2kb User : 公孙齐桓
[VHDL-FPGA-Verilog] alarm-clock DL : 0: 该代码用VHDL实现了闹钟的定时和提醒功能。里面包含四部分代码，分别实现了60，30，2分频；键盘控制；外围控制；用quartus2软件就可以打开，压缩包中附有四个代码的仿真结果。-The VHDL code used to achieve the alarm clock to remind the timing and function. Code which contains four parts, namely a frequency 60,30,2 keyboard control external control quartus2 software can be used to open, compressed package code with the simulation results of four.
Date : 2025-12-25 Size : 18kb User : 杨帆
[VHDL-FPGA-Verilog] clock DL : 0: 这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.
Date : 2025-12-25 Size : 1017kb User : ryan
[VHDL-FPGA-Verilog] clock DL : 0: 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
Date : 2025-12-25 Size : 2.96mb User : 陈涵
[VHDL-FPGA-Verilog] clock DL : 0: 多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
Date : 2025-12-25 Size : 961kb User : Stone Lei
[VHDL-FPGA-Verilog] alarm-clock DL : 0: Final project datasheet for alarm clock
Date : 2025-12-25 Size : 347kb User : YUHAN YAO
[VHDL-FPGA-Verilog] digital-alarm-clock DL : 0: this the main code for a digital alarm clock.-this is the main code for a digital alarm clock.
Date : 2025-12-25 Size : 2kb User : chhavi
[VHDL-FPGA-Verilog] Alarm-Clock DL : 0: VHDL开发环境下，编写的可以异步置数闹钟，需下载到特定硬件后，方可实现功能。-VHDL development environment, written asynchronously set the number of alarm clock, need to download to a specific hardware only after the realization of the function.
Date : 2025-12-25 Size : 743kb User : 孙佳婷
[VHDL-FPGA-Verilog] Alarm_Clock DL : 0: alarm clock vhdl implemention
Date : 2025-12-25 Size : 361kb User : Godice

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