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[VHDL-FPGA-Verilog] AI-FSM DL : 0: 游戏AI 有限状态机的示例代码 FSM-FSM FSM FSM FSM FSM FSM FSM FSM
Date : 2026-01-10 Size : 1.56mb User : 帝林
[VHDL-FPGA-Verilog] MicroBlaze DL : 0: linhta linhtinh chomaychet ai bao doi vipmember
Date : 2026-01-10 Size : 3.79mb User : Phuong
[VHDL-FPGA-Verilog] N_C DL : 0: Medium module for calcilating Modular Multiplication by Montgomery algorithm. q = (x0 + ai*b0)*m_sh. It calculate m_sh. For it it need the LSB byte of module. My E-mail: suhrob106@rambler.ru
Date : 2026-01-10 Size : 2kb User : Suhrob
[VHDL-FPGA-Verilog] rel_08_done DL : 0: 修改自OpenCores的黑白棋游戏代码。采用VGA输出显示，PS2键盘（W、A、S、D、回车）输入控制，实现AI，LED灯指示是否游戏结束，VGA显示频率25MHz，系统频率50MHz，经过Cyclone IV芯片EP4CE115F29C7N的板级调试，实现全部功能，文件夹下有rtl源代码，管脚定义pin文件，和可以直接进行JTAG烧写和E2PROM烧写的pof和sof文件，-Modified from OpenCores Othello game code. Using the VGA output display, PS2 keyboard (W, A, S, D, Enter) input control to achieve AI, LED lights indicate whether the game is over, VGA display frequency of 25MHz, the system frequency of 50MHz, after Cyclone IV chip, board-level debugging EP4CE115F29C7N to achieve full functionality, folder there rtl source code, pin definition of pin file, and can be programmed and the JTAG programming of pof and E2PROM sof file,
Date : 2026-01-10 Size : 247kb User : 诗律
[VHDL-FPGA-Verilog] Four-bit-signed-number-division DL : 0: 设计四位定点有符号整数除法器（op=ai÷bi），软件仿真通过后下载到FPGA板子进行验证 [具体要求] 1、使用clock为输入时钟信号，其频率为50MHz 2、使用拨码开关sw7~sw4为被除数ai，其中sw7为MSB(高位)，sw4为LSB(低位) 3、使用拨码开关sw3~sw0为除数bi，其中sw3为MSB，sw0为LSB 4、使用按钮btn<0>作为输入确定信号，在每次改变输入时按下按钮得到输出结果 5、以LED7~4为所得商op，LED3为MSB，灯亮代表该位为1. 6、以LED3~0为所得余数，LED7为MSB 7、若除数为0，则led7闪烁（闪烁频率自定义，以肉眼能分辨为准），led6~0熄灭 -Design of four sentinel signed integer divider (op = aibi), the software downloaded to the FPGA board through simulation to validate [the specific requirements] 1, using the clock as an input clock signal having a frequency of 50MHz 2, using a DIP switch sw7 ~ sw4 as dividend ai, which sw7 is MSB (high), sw4 for the LSB (low) 3, using DIP switches sw3 ~ sw0 divisor bi, where sw3 is MSB, sw0 for the LSB 4, using the buttons btn < 0> determining the signal as an input, press the Enter button at each change to get the output 5 to LED7 ~ 4 as the quotient op, LED3 is MSB, lights representing the bit is 1.6 to LED3 ~ 0 is the proceeds of the remainder, LED7 the MSB 7, if the divisor is zero, then led7 flashing (frequency custom, to the naked eye can distinguish prevail), led6 ~ 0 Off
Date : 2026-01-10 Size : 4kb User : 刘东辉
[VHDL-FPGA-Verilog] TEST1 DL : 0: 在本实验中，用三个按键开关来表示 1 位全加器的三个输入（ Ai、 Bi、 Ci）；用二个 LED 来表示 1 位全加器的二个输出（ Si， C）。通过输入不同的值来观察输入的结果与 1 位全加器的真值表（表 1-1）是否一致。-In this experiment, three button switches to represent three input a full adder (Ai, Bi, Ci) two by two LED to indicate output a full adder (Si, C). By entering different values and observe the results entered a full-adder truth table (Table 1-1) are the same.
Date : 2026-01-10 Size : 273kb User : 小方