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[VHDL-FPGA-Verilog] s3c2410_code_Test DL : 0: s3c2410开发板的测试代码,包括lcd，led，button，中断测试等-S3C2410 development board of the test code, including lcd, led, button, interrupt testing
Date : 2025-12-23 Size : 1.98mb User : wenger
[VHDL-FPGA-Verilog] SRAM_with_con DL : 0: 带有控制器的SRAM，提供一个地址选通脉冲ADS，一个读/写信号R_W,一个时钟信号和复位信号，包含了测试文件。-Controller with the SRAM, providing a strobe pulse Address ADS, a read/write signal R_W, a clock signal and reset signal, including the test documents.
Date : 2025-12-23 Size : 3kb User : isaac
[VHDL-FPGA-Verilog] fpga_arm DL : 0: arm和fpga一起使用，ADS，文档和代码-fpga use arm and, ADS, documentation and code
Date : 2025-12-23 Size : 708kb User : andy
[VHDL-FPGA-Verilog] main DL : 0: 这是一个在ADS环境下，在LPC2132上面调试成功的一个关于UART 中断方式运行的程序-This is an ADS environment, the successful commissioning of the above in the LPC2132 UART interrupt a run on the program
Date : 2025-12-23 Size : 1kb User : 曹小强
[VHDL-FPGA-Verilog] pcirw DL : 0: quartusII环境下实现FPGA与PCI9054通信。根据PCI9054规范控制lhold、lholda、ads、blast、lbe、lwr等握手信号的时序，可完成上位机通过PCI总线读写FPGA本地地址空间的功能- Communication between FPGA and PCI9054 in QuartusII IDE.Implementation for the timing of handshake signals such as lhold, lholda, ads,blast,lbe,lwr etc.according to the specification of PCI9054 and fullfil the function of reading/writing data from/to local address of FPGA through PCI bus.
Date : 2025-12-23 Size : 1kb User :
[VHDL-FPGA-Verilog] ADS DL : 0: traffic light controller vhdl code
Date : 2025-12-23 Size : 1.56mb User : mozzy
[VHDL-FPGA-Verilog] code_ADS_B DL : 0: ADS-B发射端RS编码、成帧及相关接口控制代码，通过过板卡测试及验证！-ADS-B transmit side RS coding, framing, and interface control code, through the testing and verification of board
Date : 2025-12-23 Size : 15kb User : wzl
[VHDL-FPGA-Verilog] ADC-ADS7230 DL : 0: ADC ADS7230 - ADC module in VHDL for ADS 7230 (Texas Instruments)
Date : 2025-12-23 Size : 2kb User : Alex