Search - access C

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[VHDL-FPGA-Verilog] traffic_1112 DL : 0: 一个交通灯的vhdl语言实现用ＶＣ的　　１．在指定的文件夹内查找某个文件　　　　　２．获取系统文件夹的路径，要求显示windows system temp 当前目录的路径Ｃ语言　　跳马问题：在５＊５的棋盘上，以编号为１的点出发，按日只跳马，要求不重复地跳所有位置，求出符合规则所有跳马的方案　　　　１　　６　　１５　　１０　　２１　　　　１４　９　　２０　　５　　　１６　　　　１９　２　　７　　　２２　　１１　　　　８　　１３　２４　　１７　　４　　　　２５　１８　３　　　１２　　２３ -a traffic light VHDL language of a VC. The designated folders to search within a document 2. Access to the system folder path, requested that the current windows system temp directory path C language vault : 5* 5 in the chessboard to the No. 1 starting point, the only daily vault and asked not to repeat all locations to jump to get in line with all rules of the program vault 1 6 15 10 21 14 9 20 5 16 19 2 7 22 11 8 13 24 17 4 25 18 3 12 23
Date : 2025-12-22 Size : 1kb User : 小三
[VHDL-FPGA-Verilog] Game_HLD3Core(400)_(C) DL : 0: 接VGA 显示器和鼠标，可以使用鼠标完成弹球游戏-access VGA display and mouse, you can use the mouse to complete Billiard games
Date : 2025-12-22 Size : 982kb User : fanbo
[VHDL-FPGA-Verilog] work3CNT4BDECL7S DL : 0: 7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
Date : 2025-12-22 Size : 81kb User : lkiwood
[VHDL-FPGA-Verilog] qi-duan-yi-ma-qi DL : 0: 七段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是2进制的，所以输出表达都是16进制的，为了满足16进制数的译码显示，最方便的方法就是利用译码程序在FPGA\CPLD中来实现。本实验作为7段译码器，输出信号LED7S的7位分别是g、f、e、d、c、b、a，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别为1、1、0、1、1、1、0、1。接有高电平段发亮，于是数码管显示“5”。-Seven-Segment is a pure combinational circuit, usually small-scale special IC, such as 74 or 4000 Series devices only for decimal BCD decoding, digital systems, however data processing and operations are binary, so the output expression hexadecimal, in order to meet the decoding of the hex number display, the most convenient way is to use a decoding program to implement in the FPGA \ CPLD. In this study, as a 7-segment decoder, the output signal LED7S 7 g, f, e, d, c, b, a, high in the left, low on the right. For example, when LED7S output for " 1101101" digital tube 7 paragraph g, f, e, d, c, b, a, respectively 1,1,0,1,1,1,0,1. Access the high level segment shiny, so the digital display " 5" .
Date : 2025-12-22 Size : 3kb User : xuling