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[VHDL-FPGA-Verilog] I2C_1.1 DL : 0: Simple I2C controller -- 1) No multimaster -- 2) No slave mode -- 3) No fifo s -- -- notes: -- Every command is acknowledged. Do not set a new command before previous is acknowledged. -- Dout is available 1 clock cycle later as cmd_ack -Simple I2C controller-- 1) No multimaster-- 2) No slave mode-- 3) No fifo's---- notes :-- Every command is acknowledged. Do not set a ne w command before previous is acknowledged.-- D is available out a clock cycle later as cmd_ack
Date : 2025-12-29 Size : 3kb User : 郑开科
[VHDL-FPGA-Verilog] All_Digital_DC2DC_Converters_on_FPGA DL : 0: The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. In this paper, based on the FPGA platform, The theoretical analysis, characteristics, simulation and design consideration are given. The methods to implement the digital DC/DC Converters have been researched. The function module, state machine of digital DC/DC controller and high resolution DPWM with Sigma- Delta dither has been introduced. They are verified by experiments on a 20 W, 300 KHz non-isolated synchronous buck converters.
Date : 2025-12-29 Size : 113kb User : gsbnd
[VHDL-FPGA-Verilog] Traffic_llight_controller DL : 0: Consider the following variation on the traffic light controller problem. A North-South road intersects an East-West road. In addition to the Red/Yellow/Green traffic lights, the N-S road has green left-turn arrows. The arrows work as follows. With the traffic lights red in all direction, the N-S left turn arrows are illuminated Green. Then they turn yellow and finally they turn red. At this point, the N-S lights cycle Green/Yellow/Red. In the N-S direction, the Green Arrow time is 16 seconds and the Yellow Arrow time is 8 s. Overlapping with this is Red light time, which is 88 s. The Green light time is 24 s and the Yellow light time is 8 s. The Red Arrow time is what is left after the other arrows have been illuminated within the N-S cycle. The E-W lights are: Red 56 s, Green 56 s, and Yellow 8 s. -Consider the following variation on the traffic light controller problem. A North-South road intersects an East-West road. In addition to the Red/Yellow/Green traffic lights, the N-S road has green left-turn arrows. The arrows work as follows. With the traffic lights red in all direction, the N-S left turn arrows are illuminated Green. Then they turn yellow and finally they turn red. At this point, the N-S lights cycle Green/Yellow/Red. In the N-S direction, the Green Arrow time is 16 seconds and the Yellow Arrow time is 8 s. Overlapping with this is Red light time, which is 88 s. The Green light time is 24 s and the Yellow light time is 8 s. The Red Arrow time is what is left after the other arrows have been illuminated within the N-S cycle. The E-W lights are: Red 56 s, Green 56 s, and Yellow 8 s.
Date : 2025-12-29 Size : 6kb User : deepa
[VHDL-FPGA-Verilog] ActelFPGA_HE_ApplicationNote DL : 0: 在手持式设备的应用中(包括智能电话、相机和 MP3 播放器)，用户大多考虑低功耗、小尺寸，整个系统中除了处理器外，往往需要提供多种通信接口与存储器接口，用于实现对硬盘、SD 卡、CF 卡以及 USB 的通信等，用 FPGA 来实现这些接口将会是一种理想的解决方案。本方案采用 Actel 低功耗的 IGLOO 系列作为处理器(PXA270 或 ARM)的桥接器件和设备控制器，不仅能够大大简化处理器设计的复杂度，而且 IGLOO 的超低功耗 (最小 5μ W)以及超小封装(4mm*4mm)给手持式产品带来了前所未有的。 -In the application of handheld devices (including smart phone, camera and MP3 players), users are considering low-power, Small size, the whole system in addition to the processor, usually need to provide various communication interface and storage interface, used to implement Hard disk, SD card, CF card and USB communication, etc, to realize these interfaces with FPGA will be an ideal solution Scheme. The scheme adopts Actel IGLOO of low power consumption PXA270 processor (series as a bridge or ARM) devices and Equipment controller, can not only greatly simplified, and the complexity of the processor design IGLOO of low power consumption (minimum 5 mu W) and small package (4mm 4mm*) for handheld product has brought an unprecedented.
Date : 2025-12-29 Size : 237kb User : zxx359654879
[VHDL-FPGA-Verilog] led_control DL : 0: 本实验箱采用的液晶显示屏内置的控制器为SED1520，点阵为122×32，需要两片SED1520组成，由E1，E2分别选通，以控制显示屏的左右两半屏。图形液晶显示模块有两种连接方式，一种为直接访问方式，一种为间接访问方式。本实验采用直接控制方式。直接控制方式就是将液晶显示模块的接口作为存储器或I/O设备直接挂在计算机总线上。计算机通过地址译码器控制E1和E2的选通；读/写操作信号R/W有地址线A1 控制，命令/数据寄存器选择信号由地址线A0控制。 -The experimental box with built-in LCD controller for the SED1520, lattice is 122 × 32, needs two SED1520 formed by the E1, E2, respectively gating to control the display of about two and a half screen. Graphic LCD module has two connections, one for the direct access method, an indirect access. In this study the direct control mode. Direct control method is to interface LCD module as memory or I/O devices directly linked to the computer bus. Computer controlled by address decoder strobe E1 and E2 read/write signal R/W control the address lines A1, command/data register select control signal from the address line A0.
Date : 2025-12-29 Size : 1.15mb User : yangxiao
[VHDL-FPGA-Verilog] FPGA-Kai-Fa-Ban.REV2.0 DL : 0: 本产品教程与注亍NIOS Ⅱ嵌入式开収,主要由C诧言开収,因此,打好C诧言的基础很重要,在此推荐一本《C程序设计诧言》(第2版),英文名为《The C Programming Language》(Second Edition),该书是由C诧言的设计者Brian W.Kernighan和Dennis M.Ritchie编写的一部介绍标准C诧言及其程序设计方法的权威性经典著作。全面、系统地讱述了C诧言的各个特性及程序设计的基本方法，包括基本概念，类型和表达式、控制流、函数不程序结构、指针不数组、结构、输入不输出、UNIX系统接口、标准库等内容-Note this product tutorials and close right foot to open the embedded NIOS Ⅱ, made mainly by the C surprised to open closed, therefore, to lay the basis for C is very important words surprised at this recommendation a " C Programming surprised Introduction" (2nd edition) , the English called " The C Programming Language" (Second Edition), surprised the book made by the designers of C Brian W. Kernighan and Dennis M. Ritchie introduced a prepared statement surprised the standard C programming method and its authority classics. Comprehensive, systematic Ren surprised statement describes the various characteristics of C and the basic method of programming, including basic concepts, types and expressions, control flow, function does not program structure, pointers are not arrays, structures, input not output, UNIX System Interface , the standard library, etc.
Date : 2025-12-29 Size : 1.86mb User : liyucai
[VHDL-FPGA-Verilog] linijka DL : 0: linijka--pomiarowa.rar Generalnie w odbiorniku nie ma wiekszel filozofi. Sa sygnaly z 2 czujnikow, zaluzmy ze czujnik 1 jest po lewej stronie, 2 po prawej. Czyli (zgodnie z tym opisem www.elektroda.pl/rtvforum/topic1132763.html) jeli z 2-giego czujnika dochodzi sygnal wysoki a na 1 pojawia sie zbocze narastajace to wykrywany jest ruch w prawo o 1 krok (jednostke) - odwrotnie dla drugiego (1 stan wysoki, 2 zbocze narastajace to ruch w lewo). Uklad jest taktowany zegarem 60 MHz (dlatego ze maksymalna czestotliwosc wykrywanych impulsow z czujnikow to 30MHz, tak wiec czestotliwosc ukladu powinna byc 2 razy wieksza - ale to moze pan dopytac najwyzej prowadzecego). Jest modul test ktory zadaje wymuszenia (sekwencje impulsow dla ruchu w prwo i wlewo i sprawdza odpowiedz) -linijka--pomiarowa.rar Generalnie w odbiorniku nie ma wiekszel filozofi. Sa sygnaly z 2 czujnikow, zaluzmy ze czujnik 1 jest po lewej stronie, 2 po prawej. Czyli (zgodnie z tym opisem www.elektroda.pl/rtvforum/topic1132763.html) jeli z 2-giego czujnika dochodzi sygnal wysoki a na 1 pojawia sie zbocze narastajace to wykrywany jest ruch w prawo o 1 krok (jednostke) - odwrotnie dla drugiego (1 stan wysoki, 2 zbocze narastajace to ruch w lewo). Uklad jest taktowany zegarem 60 MHz (dlatego ze maksymalna czestotliwosc wykrywanych impulsow z czujnikow to 30MHz, tak wiec czestotliwosc ukladu powinna byc 2 razy wieksza - ale to moze pan dopytac najwyzej prowadzecego). Jest modul test ktory zadaje wymuszenia (sekwencje impulsow dla ruchu w prwo i wlewo i sprawdza odpowiedz)
Date : 2025-12-29 Size : 36kb User : maniek
[VHDL-FPGA-Verilog] Interactive-state-machine DL : 0: 交互状态机建模，交互状态机能够使用通过公共寄存器通信的独立的a l w a y s语句进行描述。示的两个交互进程的状态图， T X是一个发送器， M P是一个微处理器。如果进程T X不忙，进程M P将要发送的数据放置在数据总线上，然后向进程T X发送信号L o a d T X，通知其装载数据并开始发送数据。进程T X在数据传送期间设置T X B u s y表明其处于忙状态，不能从进程M P接收任何进一步的数据。-Interactive state machine modeling, interactive state machine can be used to communicate through the public register statements describe independent always. Shows the state diagram of two interacting processes, TX is a transmitter, MP is a microprocessor. If the process TX is not busy, the process of MP will be placed in the data to be transmitted on the data bus, and then send a signal to process TX L oad TX, notify the load data and begin sending data. TX during the data transfer process set TXB usy that it is busy, the process of MP can not receive any further data.
Date : 2025-12-29 Size : 4kb User : 小模子
[VHDL-FPGA-Verilog] rel_08_done DL : 0: 修改自OpenCores的黑白棋游戏代码。采用VGA输出显示，PS2键盘（W、A、S、D、回车）输入控制，实现AI，LED灯指示是否游戏结束，VGA显示频率25MHz，系统频率50MHz，经过Cyclone IV芯片EP4CE115F29C7N的板级调试，实现全部功能，文件夹下有rtl源代码，管脚定义pin文件，和可以直接进行JTAG烧写和E2PROM烧写的pof和sof文件，-Modified from OpenCores Othello game code. Using the VGA output display, PS2 keyboard (W, A, S, D, Enter) input control to achieve AI, LED lights indicate whether the game is over, VGA display frequency of 25MHz, the system frequency of 50MHz, after Cyclone IV chip, board-level debugging EP4CE115F29C7N to achieve full functionality, folder there rtl source code, pin definition of pin file, and can be programmed and the JTAG programming of pof and E2PROM sof file,
Date : 2025-12-29 Size : 247kb User : 诗律
[VHDL-FPGA-Verilog] AssignmentP4 DL : 0: Assignment 4: 1. Analyze and simulate the following code lists (code1 and code 2) with the same input signals shown below by presenting POW and OL. If the data type of “a, b, c, d, u, v, w, x, y, z” is declared as std_logic, what will the simulation outputs be changed?
Date : 2025-12-29 Size : 168kb User : 魏攸
[VHDL-FPGA-Verilog] clock DL : 0: clk：标准时钟信号，本例中，其频率为4Hz； clk_1k：产生闹铃音、报时音的时钟信号，本例中其频率为1024Hz； mode：功能控制信号；为0：计时功能；为1：闹钟功能；为2：手动校时功能； turn：接按键，在手动校时功能时，选择是调整小时，还是分钟；若长时间按住该键，还可使秒信号清零，用于精确调时； change：接按键，手动调整时，每按一次，计数器加1；如果长按，则连续快速加1，用于快速调时和定时； hour,min,sec ：此三信号分别输出并显示时、分、秒信号，皆采用BCD码计数，分别驱动6个数码管显示时间； alert：输出到扬声器的信号，用于产生闹铃音和报时音；闹铃音为持续20秒的急促的"嘀嘀嘀"音，若按住"change"键，则可屏蔽该音；整点报时音为"嘀嘀嘀嘀-嘟"四短一长音； LD_alert：接发光二极管，指示是否设置了闹钟功能； LD_hour：接发光二极管，指示当前调整的是小时信号； LD_min：接发光二极管，指示当前调整的是分钟信号。-clk: standard clock signal, in this case, the frequency of 4Hz clk_1k: generate the alarm sound, chime sound clock signal, in this case the frequency of 1024Hz mode: Functional control signal 0: Chronograph function 1: The alarm clock function 2: Manually school-time functionality turn: access keys manually school function, the choice is to adjust hours or minutes If you long press the key, also make clear of the second signal for precise tone change: access key, and manually adjust each time you press the counter plus 1 If long, then in quick succession plus one for fast tune and timing hour, min, sec: This signal is output and display hours, minutes and seconds signal, All use a BCD count, drive six digital display time alert: Output signal to the speaker used to generate the alarm tone chime sound The alarm tone for the last 20 seconds of rapid beeping beep "tone, if hold down the" change "button, Can be shielded from the sound the whole point timekeeping w
Date : 2025-12-29 Size : 480kb User : happy
[VHDL-FPGA-Verilog] w DL : 0: VHDL编写的一个简单的数码管扫描电路程序-VHDL prepared a simple digital scanning circuit program
Date : 2025-12-29 Size : 593kb User : 基哥
[VHDL-FPGA-Verilog] vga_snake DL : 0: 这是一个基于VGA显示和PS2键盘的贪吃蛇游戏进入时屏幕提示“enter to play”，W,S,A,D四个CS游戏方向键，可按下P(PAUSE)暂停，进入选择关级，然后按下G（GO_ON）继续。游戏设置9关，每关吃下21个苹果即可过关。蛇的移动速度随着关级增加。每次按下按键都会有蜂鸣器提示声（暂时没有设置声音开关按钮，有兴趣的同学可以自己设计一下）。-This is a VGA-based display and PS2 keyboard greedy snake game when the screen prompts enter to play , W, S, A, D four CS game arrow keys, you can press P (PAUSE) to pause, enter the selection off Level, then press G (GO_ON) to continue. Game set 9 off, each time to eat 21 apples can go through. The speed of movement of the snake increases with the level. Each time you press the button will have a buzzer sound (not set the sound switch button, interested students can design their own).
Date : 2025-12-29 Size : 14.41mb User : 谢炀