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[VHDL-FPGA-Verilog] 16qam vhdl DL : 0: 实现16QAM系统调制仿真，附件里面WORD文档是整合的程序，其他的是源文件
Date : 2010-10-16 Size : 9.21kb User : yhyiciyuan
[VHDL-FPGA-Verilog] EDATOOL DL : 0: EDA的工具介紹(WORD檔)<沒有解壓縮密碼>-introduced EDA tools (Word stalls) lt; No extract passwords gt;
Date : 2025-12-19 Size : 16kb User : 韓堇
[VHDL-FPGA-Verilog] FSKmodemodulateVHDLprogramme DL : 0: FSK调制与解调的vhdl源代码与仿真指导，是word文档打开。-FSK modulation and demodulation of VHDL source code and simulation of the guide is the word document open.
Date : 2025-12-19 Size : 51kb User : 吴涛
[VHDL-FPGA-Verilog] cmbwordtrig DL : 0: 用于逻辑分析仪的组合字触发程序,带四级触发字和一个屏蔽字,当满足触发条件是输出高电平,复位后清零-for logic analyzer word combinations trigger procedures, with four characters and a trigger word shielding, When the trigger conditions are met output to I, after reset, reset
Date : 2025-12-19 Size : 1kb User :
[VHDL-FPGA-Verilog] DCT_vhdl DL : 0: IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable-IDCT-M is a medium speed 1D IDCT core-- it ca n accept a continuous stream of 12-bit input word 's at a rate of-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP @ ML MPEG video-- the core is 100 % synthesizable
Date : 2025-12-19 Size : 10kb User : 陈朋
[VHDL-FPGA-Verilog] DDS_Power DL : 0: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Date : 2025-12-19 Size : 16kb User : 田世坤
[VHDL-FPGA-Verilog] Eda1 DL : 0: 程序在报告中，要　用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the
Date : 2025-12-19 Size : 6kb User : haidong
[VHDL-FPGA-Verilog] EDA DL : 0: 程序在报告中，要　用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the
Date : 2025-12-19 Size : 259kb User : haidong
[VHDL-FPGA-Verilog] uartverlog DL : 0: 占用资源少的verilog HDL uart接口；采用固定波特率115200，可以修改程序中的分频来修改波特率，模式为1个启始位，8位数据位，1个停止位；带1字节缓存；当缓存空时输出空信号-Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
Date : 2025-12-19 Size : 2kb User : 张诚
[VHDL-FPGA-Verilog] lcd DL : 0: 本程序是用VHDL语言编写液晶驱动程序,实现在液晶上显示"年"字的功能.-This procedure is used VHDL language LCD drivers, realize in the liquid crystal display in the function of the word.
Date : 2025-12-19 Size : 1kb User : 何平
[VHDL-FPGA-Verilog] fpga DL : 0: fpga功能实现有限字长响应FIR 用verilog编写-FPGA functionality in response to the realization of finite word-length FIR prepared using Verilog
Date : 2025-12-19 Size : 136kb User : 吴务
[VHDL-FPGA-Verilog] dds_8bit DL : 0: rom地址宽度8位，256个正弦波数据。频率控制字可以步进，具有清零功能。-rom address the width of 8, 256 sine wave data. Frequency control word can step has cleared function.
Date : 2025-12-19 Size : 344kb User : eroad
[VHDL-FPGA-Verilog] Verilog_FIFO_ram DL : 0: 一个可以综合的Verilog 写的FIFO存储器，word格式-An integrated Verilog wrote FIFO memory, word format
Date : 2025-12-19 Size : 19kb User : hjx
[VHDL-FPGA-Verilog] VHDL DL : 0: VHDL 设计中电路简化问题的探讨 word文件-VHDL design of the circuit to simplify the problem of word document
Date : 2025-12-19 Size : 7kb User : 王分
[VHDL-FPGA-Verilog] VHDL________ DL : 0: VHDL programming samples WORD DOC FILE
Date : 2025-12-19 Size : 4kb User : kofway
[VHDL-FPGA-Verilog] asd DL : 0: 欢迎大家下载，vhdl编写的交通灯控制原代码，-Welcome everyone to download, vhdl traffic lights to control the preparation of the original code,
Date : 2025-12-19 Size : 29kb User : 蒋乃乾
[VHDL-FPGA-Verilog] pld DL : 0: 四字路口交通灯管理器的设计（含波形输出）-Management of traffic lights at the junction word design (including waveform output)
Date : 2025-12-19 Size : 107kb User : 庞永亮
[VHDL-FPGA-Verilog] traffic_lights DL : 0: Verilog语言3个程序，包括4位二进制的BCD码加法器，ALU位片，交通信号灯。既有源码也有word文档说明。-Verilog language three procedures, including 4-bit binary code of the BCD adder, ALU-bit chip, traffic lights. Only source documents that have word.
Date : 2025-12-19 Size : 1.52mb User : 郭函
[VHDL-FPGA-Verilog] barrons-word-list DL : 0: barrons word list very useful
Date : 2025-12-19 Size : 134kb User : rahul
[VHDL-FPGA-Verilog] Aword解密软件 DL : 0: 绿色在线破解WORD加密功能，经过多次使用功能正常可用。(Green online cracking WORD encryption function, after repeated use of normal function available.)
Date : 2025-12-19 Size : 3.41mb User : hnxldx

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