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[VHDL-FPGA-Verilog] Convolutional encoding and Viterbi decoding with k DL : 0: 卷积码编码和维特比解码当K为7 时供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
Date : 2026-01-12 Size : 248kb User : 周小川
[VHDL-FPGA-Verilog] Viterbi_v DL : 0: Viterbi算法的Verilog源代码。-Viterbi Algorithm Verilog source code.
Date : 2026-01-12 Size : 11kb User : qjyong
[VHDL-FPGA-Verilog] viterbi DL : 0: VHDL 程序，实现vertibe的编码和解码。-VHDL procedures vertibe realize the encoding and decoding.
Date : 2026-01-12 Size : 2kb User : 左麟
[VHDL-FPGA-Verilog] viterbi DL : 0: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Date : 2026-01-12 Size : 61kb User : yaoyongshi
[VHDL-FPGA-Verilog] viterbi DL : 0: (2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through
Date : 2026-01-12 Size : 10kb User : rxl
[VHDL-FPGA-Verilog] Viterbi_RAKE DL : 0: 这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章，实用性很强的，在这里也感谢这篇文章的作着-This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was
Date : 2026-01-12 Size : 8.43mb User : 骆军
[VHDL-FPGA-Verilog] viterbi DL : 0: 卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
Date : 2026-01-12 Size : 250kb User : mediative
[VHDL-FPGA-Verilog] viterbi_node_sync_design DL : 0: 一个完整的viterbi译码程序和测试的程序-A complete viterbi decoding procedures and test procedures
Date : 2026-01-12 Size : 268kb User : deng
[VHDL-FPGA-Verilog] ViterbiDecodeK9R12HardDecision DL : 0: viterbi 硬判决译码，基本实现了（2，1，9）卷积码的硬判决译码，用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
Date : 2026-01-12 Size : 12kb User : maojunling
[VHDL-FPGA-Verilog] husw DL : 0: 用VHDL语言设计维特比解码器是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
Date : 2026-01-12 Size : 1kb User : hsw0320
[VHDL-FPGA-Verilog] viterbi DL : 0: 这是一个用VERILOG HDL语言编写的viterbi译码程序-This is a language VERILOG HDL by the viterbi decoding process
Date : 2026-01-12 Size : 2kb User : chenxiaoming
[VHDL-FPGA-Verilog] VB_decode DL : 0: Viterbi译码的VHDL代码，并且附有详细说明-Viterbi decoding of the VHDL code, and accompanied by a detailed description
Date : 2026-01-12 Size : 61kb User : 陈娟
[VHDL-FPGA-Verilog] Viterbi DL : 0: 实现VHDL的维特比译码 -VHDL Viterbi decoding to achieveVHDL Viterbi decoding to achieve
Date : 2026-01-12 Size : 145kb User : 飞熊
[VHDL-FPGA-Verilog] viterbi DL : 0: 硬判决viterbi译码的硬件实现，通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
Date : 2026-01-12 Size : 90kb User : Fengxiaodong
[VHDL-FPGA-Verilog] Viterbi_check DL : 0: It is a verilog code for viterbi decoding with trellis diagram
Date : 2026-01-12 Size : 400kb User : Murthy
[VHDL-FPGA-Verilog] Viterbi_verilog DL : 0: 在ISE环境下用Verilog语言编写的卷积码程序及Viterbi译码程序-Under the ISE Verilog language with procedures and Viterbi convolutional code decoding program
Date : 2026-01-12 Size : 4.88mb User : lxz
[VHDL-FPGA-Verilog] viterbi DL : 0: 高效率的viterbi译码，对通信中的卷积码进行译码-Efficient viterbi decoding of communications for decoding convolutional codes
Date : 2026-01-12 Size : 2kb User : 顾冰
[VHDL-FPGA-Verilog] finial_test DL : 0: 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
Date : 2026-01-12 Size : 5.33mb User : lxz
[VHDL-FPGA-Verilog] encoder DL : 0: 802.11a卷积码的实现，使用公式133和177，可以用标准viterbi解码-802.11a convolutional code to achieve, using the formula 133 and 177, you can use standard viterbi decoding
Date : 2026-01-12 Size : 1kb User : Team
[VHDL-FPGA-Verilog] Design-Space-Exploration-of-Hard-Decision-Viterbi DL : 0: Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation
Date : 2026-01-12 Size : 1.04mb User : saravanan

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