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[VHDL-FPGA-Verilog] fifo数据缓冲器的vhdl源程序 DL : 0: 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-Bianlegan 8* 8 of the data buffer fifo VHDL source, after quartusII4.2 compiler successful procedures. . Hope you enjoy the exchanges
Date : 2026-01-02 Size : 1kb User : 夏社
[VHDL-FPGA-Verilog] vhdl_fifo DL : 0: 用vhdl编写的fifo队列.可以在maxplus2平台上使用.-using VHDL fifo prepared by the cohort. Maxplus2 platform can be used.
Date : 2026-01-02 Size : 302kb User : 蔡庆重
[VHDL-FPGA-Verilog] VHDL.fifo DL : 0: 在网上找到的通用存储器vhdl代码库，觉得挺好用的。-the Internet to find the common memory vhdl code library, feeling very good use.
Date : 2026-01-02 Size : 1.12mb User : 黎莉
[VHDL-FPGA-Verilog] FIFO DL : 0: verilog开发的FIFO，经过验证，有完整版本的测试程序，经典之作-Verilog development FIFO, after verification, a complete version of the test procedure, classic
Date : 2026-01-02 Size : 2kb User : 屠宁杰
[VHDL-FPGA-Verilog] FIFO DL : 1: 异步FIFO verilog实现异步FIFO verilog实现 -Asynchronous FIFO verilog realize realize asynchronous FIFO verilog
Date : 2026-01-02 Size : 4kb User : lyjIC
[VHDL-FPGA-Verilog] FIFO DL : 0: VHDL源代码程序，使用VHDL语言编写，一个FIFO的代码实现工程-VHDL source code, the use of VHDL language, a FIFO realize the code works
Date : 2026-01-02 Size : 3kb User : 罗兰
[VHDL-FPGA-Verilog] FIFO DL : 0: FIFO的源代码，对FIFO设计有帮助，有借鉴意义，帮助学习VHDL编程-FIFO of the source code, on the FIFO design help, there is reference to help learn VHDL programming
Date : 2026-01-02 Size : 1kb User : 胡清泉
[VHDL-FPGA-Verilog] fifo-1117 DL : 0: 这是异步FIFO的VHDL实现代码，已经在FPGA上通过实践证明，运行状态良好-This is the asynchronous FIFO realize the VHDL code, the FPGA has been proved through practice, running in good condition
Date : 2026-01-02 Size : 20kb User : 杨宇
[VHDL-FPGA-Verilog] fifo DL : 0: 使用VHDL编程的异步FIFO程序经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger
Date : 2026-01-02 Size : 128kb User : 张星
[VHDL-FPGA-Verilog] fifo DL : 1: 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
Date : 2026-01-02 Size : 1kb User : shili
[VHDL-FPGA-Verilog] FIFO DL : 0: 用VHDL语言编写的实现FIFO的设计，经编译下载成功-VHDL language used to achieve FIFO design, by the compiler download success
Date : 2026-01-02 Size : 65kb User : henry
[VHDL-FPGA-Verilog] RS232uart(VHDL) DL : 0: 256字节深度的RS232串口程序,共分4个模块,顶层文件\FIFO程序\串口收和串口发.经过测试已用于产品.可靠!-Depth of 256-byte Serial RS232 procedures, divided into four modules, top-level document procedures FIFO serial and serial-fat collection. After the test has been used in products. Reliable!
Date : 2026-01-02 Size : 5kb User : 温海龙
[VHDL-FPGA-Verilog] FIFO DL : 0: 异步FIFO的实现，可综合，可验证] keywords:almost_full,full,almost_empty,empty-The realization of asynchronous FIFO can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty
Date : 2026-01-02 Size : 1kb User : ly
[VHDL-FPGA-Verilog] fifo DL : 0: 此程序为存储器常用的FIFO（先入先出），程序中没有指明位宽，这样更适合于初学者进行套用-This process commonly used for the memory FIFO (FIFO), the procedure is not specified bit, so more suitable for beginners to apply
Date : 2026-01-02 Size : 1kb User : zhaohongliang
[VHDL-FPGA-Verilog] Fifo DL : 0: 一个FIFO源代码，基于Altera FPGA-A FIFO source code, based on Altera FPGA
Date : 2026-01-02 Size : 1kb User : jiashengwen
[VHDL-FPGA-Verilog] FIFO DL : 0: 一个用VHDL源码编写的先进先出(FIFO)缓冲器模块.可以进行FIFO的仿真验证-A source prepared by VHDL FIFO (FIFO) buffer module. Can verify FIFO simulation
Date : 2026-01-02 Size : 2kb User : falcon_cq
[VHDL-FPGA-Verilog] fpga.fifo DL : 0: 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the phase and frequency offset between different clock domain in communication area .In this paper, an FIFO module is designed using Gray convert technology and dual-port ram , which realizing scatheless transmit between different clock domain. The advances of Gray (Only one bit changes between neighboring two clock ) improves the reliability and anti-jamming capability of the system. And the system can work normally in the bad condition which the phase and frequency offset target to 300PPM. It is proved by work that the FIFO module can fulfill the demands of real-time of data transmitting system, and the module is powerful enough for more data process in the future.
Date : 2026-01-02 Size : 80kb User : 雷志
[VHDL-FPGA-Verilog] fifo-interface DL : 0: fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
Date : 2026-01-02 Size : 1kb User : sunbaoyu
[VHDL-FPGA-Verilog] FIFO DL : 0: 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
Date : 2026-01-02 Size : 4kb User : 邵捷
[VHDL-FPGA-Verilog] fifo DL : 0: 先进先出存储电路fifo，实现队列存储结构-xianjin xianchu chunchu dianlu fifo
Date : 2026-01-02 Size : 478kb User : 623902748

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