Search - VC 6.0

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[VHDL-FPGA-Verilog] traffic_1112 DL : 0: 一个交通灯的vhdl语言实现用ＶＣ的　　１．在指定的文件夹内查找某个文件　　　　　２．获取系统文件夹的路径，要求显示windows system temp 当前目录的路径Ｃ语言　　跳马问题：在５＊５的棋盘上，以编号为１的点出发，按日只跳马，要求不重复地跳所有位置，求出符合规则所有跳马的方案　　　　１　　６　　１５　　１０　　２１　　　　１４　９　　２０　　５　　　１６　　　　１９　２　　７　　　２２　　１１　　　　８　　１３　２４　　１７　　４　　　　２５　１８　３　　　１２　　２３ -a traffic light VHDL language of a VC. The designated folders to search within a document 2. Access to the system folder path, requested that the current windows system temp directory path C language vault : 5* 5 in the chessboard to the No. 1 starting point, the only daily vault and asked not to repeat all locations to jump to get in line with all rules of the program vault 1 6 15 10 21 14 9 20 5 16 19 2 7 22 11 8 13 24 17 4 25 18 3 12 23
Date : 2025-12-17 Size : 1kb User : 小三
[VHDL-FPGA-Verilog] dds DL : 0: 利用EDA硬件描述语言来实现DDS功能，利用VC++6.0实现sinx,cosx数据的采集，用quart2软件为载体实现-The use of EDA hardware description language to achieve the DDS functions, using VC++6.0 to achieve sinx, cosx data collection, software used as the carrier to achieve quart2
Date : 2025-12-17 Size : 727kb User : 游智超
[VHDL-FPGA-Verilog] systemc-2.2.0 DL : 0: 这个是systemC在VC下编译后的文件，响应的运行时 include systemc-2.2.0\src systemc.h 都文件。并且建立项目时把SystemC.lib加入项目中即可编译SystemC-This is the systemC after VC complie, you can include the systemc-2.2.0\src systemc.h file and add SystemC.lib to your project .
Date : 2025-12-17 Size : 16.81mb User : wyb527
[VHDL-FPGA-Verilog] VC DL : 0: 用Verilog语言实现16点的FFT运算.用Verilog语言实现16点的FFT运算。用Verilog语言实现16点的FFT运算。-Verilog language by 16 points in the FFT computation. Verilog language by 16 points in the FFT computation. Verilog language by 16 points in the FFT computation.
Date : 2025-12-17 Size : 5kb User : 懂郑华
[VHDL-FPGA-Verilog] Dragon-Heart_VERILOG.doc DL : 0: 神州龙芯cpu的verilog设计规范，本规范适用于下列三种 Verilog代码文件的编写：1）可综合逻辑部件；2）虚拟部件（Virtual Component--VC）；3）测试模块（testbenches）。-The verilog design specification of BLX cpu
Date : 2025-12-17 Size : 65kb User : Victor