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[VHDL-FPGA-Verilog] FIFO_BEFORE DL : 0: 是基于fpga的FIFO乒乓操作，后面是与SDRAM接口的，这样主要方便sdram的刷新-fpga is based on the FIFO Table Tennis operation, and is behind SDRAM interface, This major update to the convenience sdram
Date : 2026-01-23 Size : 207kb User : eva
[VHDL-FPGA-Verilog] wb_rtc DL : 0: // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined-//-*- Mode: Verilog-*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
Date : 2026-01-23 Size : 8kb User : 姓名
[VHDL-FPGA-Verilog] bitNode_Behaviora_VHDL DL : 0: LDPC码的消息节点（Bitnode）消息更新过程的VHDL语言实现-LDPC code of the message node (Bitnode) news update process of the VHDL language
Date : 2026-01-23 Size : 1kb User : 王明
[VHDL-FPGA-Verilog] DE2_70_TOP DL : 0: 在quartus上实现电子锁的设计，采用cyclone的板子，方便设置初始密码，更新密码-Quartus to achieve in the design of electronic locks, using cyclone of the board, easy to set the initial password, update password
Date : 2026-01-23 Size : 710kb User : 崔海
[VHDL-FPGA-Verilog] Firmware-Updater_4.3b DL : 0: update firmware 4.3 for nintendo w-update firmware 4.3 for nintendo wii
Date : 2026-01-23 Size : 329kb User : mario
[VHDL-FPGA-Verilog] typegame_7-26_final DL : 0: 五个字母在屏幕上下落，击中即消并更新字母，实现打字游戏-VHDL code for typegame-- when you press the right key ,than the letter on the screen will update.
Date : 2026-01-23 Size : 7.68mb User : 郑倩
[VHDL-FPGA-Verilog] XtreamWay-update DL : 0: 本次只需要升级交换板SF2300上的软件版本，升级完成并重启后SF2300会自动加载更新后的应用承载板AC2240软件在SF2300的应用维护模式appadmin下更新xway_om.zip，在SF2300的管理维护模式OMadmin下更新xway_node.zip， xw_rpc.tar.gz是用于x86刀片服务器对FPGA卡进行RPC调用的软件包软件更新方法、XtreamWay交换协议、FPGA远程调用方法等可参考附件中的说明文档 -The exchange only need to upgrade the software version on board SF2300, SF2300, after the upgrade is complete and restart the update will automatically load the application bearing plate AC2240 software application maintenance mode appadmin SF2300 to update xway_om.zip, the management mode in SF2300 OMadmin update the xway_node.zip, xw_rpc.tar.gz for x86 blade server RPC calls on the FPGA card package software update method, XtreamWay exchange protocol, FPGA remote call methods refer to the attached documentation
Date : 2026-01-23 Size : 18.57mb User : BRN
[VHDL-FPGA-Verilog] pyball DL : 0: Hex type memory file. Used to update memory in a simple MIPS processor
Date : 2026-01-23 Size : 2kb User : Peace
[VHDL-FPGA-Verilog] remoteupdatecontroller DL : 1: ALTERA CYLONEIII Remote update controller的一个实现例子，包括了通过串口读写EPCS芯片，进行远程烧写-ALTERA CYLONEIII Remote update controller example of an implementation, including read and write EPCS chip through the serial port, for remote programming
Date : 2026-01-23 Size : 890kb User : zhuying
[VHDL-FPGA-Verilog] modelsim_guide_cn DL : 0: 使用ModelSim进行设计仿真ModelSim为HDL仿真工具，我们可以利用该软件来实现对所设计的VHDL或Verilog程序进行仿真，支持IEEE常见的各种硬件描述语言标准。可以进行两种语言的混合仿真，但推荐大家只对一种语言仿真。ModelSim常见的版本分为ModelSim XE和ModelSim SE两种，ModelSim版本更新很快-Design simulation using ModelSim HDL simulator ModelSim is, we can use the software to achieve the program designed to simulate VHDL or Verilog, to support a variety of common IEEE standard hardware description language. Mixture of two languages can be simulated, but recommend only one language simulation. Common version of ModelSim and ModelSim SE ModelSim XE is divided into two types, ModelSim version update soon
Date : 2026-01-23 Size : 334kb User : 谢明
[VHDL-FPGA-Verilog] aa DL : 0: 簡易的七段猜數字，先設定所猜數字後，按下a鍵輸入，開始猜數字，每輸入兩數字後，按下a鍵確認，更新上下限。-Simple seven-segment number guessing, first set the number guessing, and then press a key to enter the start number guessing, each of the two digital input, press a button to confirm, update the upper and lower limits.
Date : 2026-01-23 Size : 642kb User : 楊承翰
[VHDL-FPGA-Verilog] writ DL : 0: GUSS里面的读模块，具有非常高的利用价值，主要就是几个参数的读更新以及输出。-Inside the GUSS read module, has very high use value, is the main parameters and output read update
Date : 2026-01-23 Size : 1kb User : luogui
[VHDL-FPGA-Verilog] version2_5_20 DL : 0: 单片机控制GSM模块实现手机功能，并有智能查询当前温度和刷新温度的功能-GSM achieve singlechip control mobile phone functions, and has an intelligent query and update the temperature function
Date : 2026-01-23 Size : 74kb User : crystalsure
[VHDL-FPGA-Verilog] lcd1602_module- DL : 0: 1602液晶的驱动代码。网上很多1602液晶的代码只是驱动液晶而已，并不能很好的动态更新数据，我在参考别人代码的基础上修改后得到这段可以动态更新数据的驱动代码。-1602 LCD driver code. 1602 online a lot of code just drive LCD only, and not a very good dynamic update data, I refer to someone else' s code to get this on the basis of the modified data can be dynamically updated driver code.
Date : 2026-01-23 Size : 1kb User : 钱芳斌
[VHDL-FPGA-Verilog] iic_88091 DL : 0: 实现88091驱动带iic驱动可以通过网管控制盘通过IIC更新配置参数-Achieve 88,091 iic driver can drive belt through the network control panel update configuration parameters through the IIC
Date : 2026-01-23 Size : 3kb User : sunisi2008
[VHDL-FPGA-Verilog] free_map DL : 0: The target is the first field so just update the pointers.
Date : 2026-01-23 Size : 4kb User : nanzgfun