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[VHDL-FPGA-Verilog] wb_rtc DL : 0: // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined-//-*- Mode: Verilog-*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
Date : 2025-12-29 Size : 8kb User : 姓名
[VHDL-FPGA-Verilog] MTDB_SYSTEM_CD_V1.0 DL : 0: ALTERA Nios II Embedded Evaluation Kit开发板制造商(terasic)提供的多媒体显示板（Terasic Multimedia Touch Panel Daughter Board (MTDB)）扩展开发包。里为有两个开源的例子 1.MTDB_SD_Card_Audio,从SD卡中读取WAV文件然后通过DA播放，这个对不SD Card的初学者非常的有用，可以知道使用FPGA SPI来读写SD CARD。 2.MTDB_Systhesizer,使用FPGA来做电子琴，要用FPGA来做合成器的看这个。国内部分地区的网络对TERASIC封杀，原因不明，这个包是使用代理下载的，非常不容易。-ALTERA Nios II Embedded Evaluation Kit development board manufacturers (terasic) to provide multi-media display boards (Terasic Multimedia Touch Panel Daughter Board (MTDB)) the expansion of the development package. Where for example there are two open source 1.MTDB_SD_Card_Audio, from the SD card and then read the WAV file to play through the DA, the SD Card for the beginner is not very useful, we can see that the use of FPGA SPI read and write to SD CARD. 2.MTDB_Systhesizer, the use of FPGA as organ, synthesizer use FPGA to do the look at this. Internal parts of the network to block TERASIC for reasons unknown, the package is downloaded using a proxy, is not easy.
Date : 2025-12-29 Size : 26.19mb User : myfingerhurt
[VHDL-FPGA-Verilog] HDLImplementationoftheVariableStepSize DL : 0: proposes a Verilog implementation of the Normalized Least Mean Square (NLMS) adaptive algorithm, having a variable step size. The envisaged application is the identification of an unknown system. First the convergence of derived LMS algorithms was analyzed in a Simulink application.
Date : 2025-12-29 Size : 218kb User : 陳柏宇
[VHDL-FPGA-Verilog] vacantfiles4 DL : 0: unknown vga files but still helpful
Date : 2025-12-29 Size : 3kb User : Enticing Fury
[VHDL-FPGA-Verilog] upload DL : 0: A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values are compacted, some of the outputs of the compactor may also take unknown values and the correctness of the compactor inputs cannot be verified at the compactor outputs. The presence of x-values hence reduces observability of (nonx) scan cells that may lead to a reduction of test quality and/or limited compaction rates
Date : 2025-12-29 Size : 33kb User : shankar.m
[VHDL-FPGA-Verilog] source DL : 0: A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values are compacted, some of the outputs of the compactor may also take unknown values and the correctness of the compactor inputs cannot be verified at the limited compaction rates
Date : 2025-12-29 Size : 10kb User : shankar.m
[VHDL-FPGA-Verilog] vhtoverilog DL : 1: A major obstacle of thge code is to convert verilog to convert an vhdl code that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values are compacted, some of the outputs of the compactor may also take unknown values and the correctness of the compactor inputs cannot be verified at the compactor outputs. The presence of x-values hence reduces observability of (nonx) scan cells that may lead to a reduction of test quality and/or limited compaction rates-A major obstacle of thge code is to convert verilog to convert an vhdl code that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values are compacted, some of the outputs of the compactor may also take unknown values and the correctness of the compactor inputs cannot be verified at the compactor outputs. The presence of x-values hence reduces observability of (nonx) scan cells that may lead to a reduction of test quality and/or limited compaction rates
Date : 2025-12-29 Size : 27.96mb User : shankar.m
[VHDL-FPGA-Verilog] vhdl-all-english DL : 0: A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with s and the correctness of the compactor inputs cannot be verified at the c limited compaction rates
Date : 2025-12-29 Size : 557kb User : shankar.m
[VHDL-FPGA-Verilog] cymometer DL : 0: 频率计，用于对一个未知频率的周期信号进行频率测量，在1s 内对信号周期进行计数，得到周期信号的频率。- Frequency meter, for an unknown frequency of the periodic signal frequency measurement, in 1s signal cycle counts, to obtain the frequency of the periodic signal.
Date : 2025-12-29 Size : 3kb User : 赵健
[VHDL-FPGA-Verilog] TX_RX DL : 0: FPGA用verilog实现串口和电脑的字符串以及单字符精准无误通信，即通过电脑向FPGA发送任一长度数据，FPGA返回PC相同的数据。波特率为9600，本例程为了得到精准的波特率使用了50M时钟的3倍频，测试可用，如有不明的地方，可以给我留言-FPGA implementation using verilog string and the computer serial port and single-character accurate communication, 9600, FPGA using verilog to achieve serial and single-character strings, and the computer communicate accurate and correct, that is, through the computer to the FPGA send any length data, FPGA return PC the same data. 9600 of the routine in order to get accurate baud using a 50M clock multiplier 3, the test can be used, if unknown place, you can give me a message
Date : 2025-12-29 Size : 3.31mb User : 冷酷豪迈