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[VHDL-FPGA-Verilog] 0917afifo_s DL : 0: 采用同步异步信号的方式，将两个CLK统一到同一个时钟下工作，用同步FIFO实现异步FIFO-Asynchronous signals using synchronous way, two a clock CLK to the same uniform to work, using synchronous FIFO Asynchronous FIFO
Date : 2025-12-29 Size : 3kb User : 范小虎
[VHDL-FPGA-Verilog] vhd_SDH DL : 0: 实现从连续传输的SDH字节流中找出帧头、提取F1字节，并按照64K速率分别串行输出F1码流及时钟，其中64K时钟要求基本均匀。文件包含报告文档-SDH transmission from a continuous stream of bytes to identify header, extract F1 bytes, respectively, in accordance with 64K-rate serial output bit stream and clock F1, of which 64K clock requires a basic uniform. File contains the report of the document
Date : 2025-12-29 Size : 69kb User : ljk05
[VHDL-FPGA-Verilog] exer2 DL : 0: 给定一个频率为33MHz的时钟，试利用该时钟得到一个基本均匀的2.048MHz时钟-Given a frequency of 33MHz clock, try to use the clock to get a basic uniform of the 2.048MHz clock
Date : 2025-12-29 Size : 27kb User : 林涛
[VHDL-FPGA-Verilog] SDH DL : 0: SDH开销的接收处理，要求： 1， A1和A2字节为帧头指示字节，A1为“11110110”，A2为“00101000”，连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机，从连续传输的SDH字节流中找出帧头。 2， E2字节为勤务话通道开销，用于公务联络语音通道，其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。（输出端口包括串行数据和64K串行时钟） -Receiving SDH overhead processing requirements: 1, A1 and A2 bytes instruction byte header, A1 is " 11110110" , A2 is " 00101000" , for three consecutive A1 bytes followed by three A2 bytes of an SDH the beginning of the frame. Asked to design a state machine, from the continuous stream of bytes in the SDH transmission header to find out. 2, E2-byte path overhead for the service, then, for the public to contact voice channels, the bit-serial rate 64KHz (8* 8K = 64). SDH byte stream request from the extraction E2 bytes, and the serial output in accordance with rates of E2 64K stream and clock, which clock requires 64K basic uniform. (Including the serial data output port and 64K serial clock)
Date : 2025-12-29 Size : 2kb User : 刘镇宇
[VHDL-FPGA-Verilog] SDHdet DL : 0: 从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。-SDH byte stream from the extracted E2 bytes, and the serial output in accordance with rates of E2 64K stream and clock, which clock 64K basic uniform requirements.
Date : 2025-12-29 Size : 1kb User : 魏可
[VHDL-FPGA-Verilog] The-Serial-communication- DL : 0: 随着多微机系统的应用和微机网络的发展，通信功能越来越显得重要。串行通信是在一根传输线上一位一位地传送信息.这根线既作数据线又作联络线。串行通信作为一种主要的通信方式，由于所用的传输线少，并且可以借助现存的电话网进行信息传送，因此特别适合于远距离传送。在串行传输中，通信双方都按通信协议进行，所谓通信协议是指通信双方的一种约定。约定对数据格式、同步方式、传送速度、传送步骤、纠错方式以及控制字符定义等问题做出统一规定，通信双方必须共同遵守。-With the application of multi-microcomputer systems and computer networks, communication becomes less important. Serial communication is a one in a transmission line to transmit information, which lines both for the data line and make contact line. Serial communication as a primary means of communication, since the transmission line with less, and can make use of existing telephone network for information transmission, it is particularly suitable for long-distance transmission. In serial transmission, the communication protocol for communication by both sides, the so-called communication protocol is an agreement the two sides. Agreement on data formats, synchronization, transmission speed, transmission procedures, error correction, and control characters are defined to make uniform provisions and other issues, communication, both parties must abide by.
Date : 2025-12-29 Size : 1kb User : 张弘
[VHDL-FPGA-Verilog] Temperature_acquisition DL : 0: 用VHDL语言在FPGA上实现了8路温度数据的采样功能。控制THS1408芯片进行AD转换，采样后存入对应的8组寄存器，并产生使能信号通知其他模块进行8路数据的统一采样。-8-channel temperature data sampling function is implemented on FPGA using VHDL language. Control THS1408 chip AD converter, and sampled into the corresponding set of registers, and generate the enable signal to inform other modules for a uniform sampling of the 8-way data.
Date : 2025-12-29 Size : 2kb User : 张明
[VHDL-FPGA-Verilog] UniformRNG DL : 0: A Uniform Random Number Generator in VHDL
Date : 2025-12-29 Size : 1kb User : Vahid
[VHDL-FPGA-Verilog] RUILI DL : 0: 均匀相位的瑞利衰落信道matlab仿真程序，并附有详细注释-Uniform phase Rayleigh fading channel matlab simulation program, together with detailed notes
Date : 2025-12-29 Size : 10kb User : 潘斯琦
[VHDL-FPGA-Verilog] IC设计流程和设计方法 DL : 0: IC的设计可以分为两个部分，分别为：前端设计（也称逻辑设计）和后端设计（也称物理设计），这两个部分并没有统一严格的界限，凡涉及到与工艺有关的设计可称为后端设计。(The design of IC can be divided into two parts: front-end design (also called logic design) and back-end design (also known as physical design). These two parts do not have a uniform and strict boundary, and the design related to process can be called back-end design.)
Date : 2025-12-29 Size : 888kb User : 叮咯咙咚呛36