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[VHDL-FPGA-Verilog] booth_mul DL : 0: 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols/unsigned multiplication of the number of binary multipliers. The multiplier used to improve the Booth algorithm, simplified some of the plot symbols expansion Wallace tree and used-ahead adder circuit to further enhance the computing speed. The multiplier can be used as embedded CPU cores multiplication modules, the entire design with VHDL.
Date : 2025-12-20 Size : 19kb User : 李鹏
[VHDL-FPGA-Verilog] jiaotd DL : 0: AD0809的源程序，能使EDA工具箱显示AD0809，具备树模转换功能-AD0809 a source, EDA can show AD0809 a toolbox, with tree-analog converter function
Date : 2025-12-20 Size : 1kb User : 安陪应
[VHDL-FPGA-Verilog] S7_UART DL : 0: 利用FPGA实现串口通信，很好的学习资料尤其是对 verilog不熟的朋友-FPGA realization of the use of serial communications, a very good learning materials especially in the wake of a friend Verilog
Date : 2025-12-20 Size : 458kb User : 杜菲
[VHDL-FPGA-Verilog] add_tree_mult DL : 0: 8位加法树乘法器,实现两个8位二进制数相乘，采用verilog hdl-8-bit adder tree multiplier, the achievement of the two 8-bit binary number multiplied, using verilog hdl
Date : 2025-12-20 Size : 1kb User : 江浩
[VHDL-FPGA-Verilog] Wallace DL : 0: 一个关于Wallace树乘法器的论文，当中展示了一种改进后的wallace树乘法器方案，相比原来占用晶体管更少，效率更高-Wallace tree multiplier on the papers, which show an improved wallace tree multiplier after the program, compared to the original transistors occupy less efficient
Date : 2025-12-20 Size : 104kb User : szx
[VHDL-FPGA-Verilog] multiply2 DL : 0: 18bit的booth乘法器采用booth2编码 Wallace压缩树以及超前进位结合进位选择的36bit高性能加法器-18bit multipliers used booth2 the booth encoding and Wallace tree compression-ahead into the location choice of high-performance 36bit adder
Date : 2025-12-20 Size : 5kb User : alex
[VHDL-FPGA-Verilog] adder DL : 0: 采用加法树流水线乘法构造八位乘法器，并分析设计的性能和结果在时钟节拍上落后的影响因素。 -Multiplication using adder tree structure line 8 multiplier, the design and analysis of the results of the performance and beat the clock on the impact of the factors behind.
Date : 2025-12-20 Size : 1.18mb User : 张炳良
[VHDL-FPGA-Verilog] brentkung_32 DL : 0: 32 bit brentkung adder tr-32 bit brentkung adder tree
Date : 2025-12-20 Size : 1kb User : suha
[VHDL-FPGA-Verilog] WallaceTreeMultiplier DL : 0: Wallace Tree Multiplier in VHDL for 4bit operation fully using structural language
Date : 2025-12-20 Size : 2.25mb User : suresh
[VHDL-FPGA-Verilog] FIR DL : 0: 用verilog设计的FIR滤波器。滤波器需要很快的处理速度，所以采用了wallace树算法，超前进位加法器-The FIR filter is designed with verilog. To improve the process speed, wallace tree and fast-carrylook-aheadarithmetic were used.
Date : 2025-12-20 Size : 317kb User : simeon chan
[VHDL-FPGA-Verilog] chengfa DL : 0: 我做的组成原理课程设计！用VHDL实现加法树的乘法。-I do the composition of the principle of curriculum design! VHDL adder tree used to achieve multiplication.
Date : 2025-12-20 Size : 40kb User : feng
[VHDL-FPGA-Verilog] add_tree DL : 0: 本程序为加法树乘法器，计算16位读写地址，应用于LCD CSTN驱动芯片设计的SRAM的读写控制-This procedure for the adder tree multiplier, calculated 16-bit read and write address, used in LCD CSTN driver IC designed to control the SRAM s read and write
Date : 2025-12-20 Size : 429kb User : 张小峰
[VHDL-FPGA-Verilog] lunwen DL : 0: 潘明海　刘英哲　于维双 (论文) 中文摘要：本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。 -Pan Minghai Liuying Zhe Yu-dimensional pairs (thesis) Chinese Abstract: This paper discusses an FPGA can be implemented on the structure of the FFT. The architecture based on pipeline architecture and fast parallel multiplier butterfly processor. Multiplier using modified Booth algorithm simplifying the partial product sign extension, use the Wallace tree and 4-2 compressor for partial product reduction. 8-point complex-point FFT as an example design of the corresponding control circuit. To complete the design using the VHDL language, and integrated into the FPGA. From the results of a comprehensive look at the structure can be XC4025E-2 with 52MHz clock on the high-speed operation. On this basis, easy to expand the structure for large point FFT operations.
Date : 2025-12-20 Size : 125kb User : culun
[VHDL-FPGA-Verilog] wallace DL : 0: This a code for wallace tree multiplier-This is a code for wallace tree multiplier
Date : 2025-12-20 Size : 4kb User : vlsi
[VHDL-FPGA-Verilog] fir_512_378_mux DL : 0: 512阶高速FIR成型滤波器，四相位复用，树形加法和多级流水线结构。-512-order high-speed FIR shaping filter, four-phase re-use, tree addition and multi-stage pipeline structure.
Date : 2025-12-20 Size : 29kb User : johnnyz
[VHDL-FPGA-Verilog] sqrt DL : 0: 树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算-Square root of the tree-type divider-type device to achieve VERILOG
Date : 2025-12-20 Size : 1kb User : 神气
[VHDL-FPGA-Verilog] WallaceTreeImplementationInVHDL DL : 0: Wallace Tree Implementation in VHDL WT is one of the fastest way to implement multiplication of numbers in hardware design. (Optimized version) Tested in Altera 3.5u board by MonteCristo (H.U.T)
Date : 2025-12-20 Size : 6kb User : montecristo
[VHDL-FPGA-Verilog] wallace DL : 0: wallace tree 用于16位乘法器的verilog 的 wallace tree代码 -wallace tree verilog file. 16bit wallace tree adder.
Date : 2025-12-20 Size : 2kb User : Zachary
[VHDL-FPGA-Verilog] SPANNING TREE ADDER 27-bit VHDL DL : 0: 27-bit spanning tree adder written in VHDL coding
Date : 2018-01-12 Size : 185.53kb User : spgp1306
[VHDL-FPGA-Verilog] SPANING_27BIT DL : 0: spanning tree adder writtern vHDL Code
Date : 2025-12-20 Size : 185kb User : GIRISH

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