Search - Serial debugging assistant

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[VHDL-FPGA-Verilog] my_uart_top DL : 0: 实现的功能如题，就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。使用的是串口UART协议进行收发数据。上位机用的是老得掉牙的串口调试助手-To achieve the functions such as title, that is, to achieve FPGA receives data from the PC, and then receive data back fat. Using a UART serial port protocol to send and receive data. PC using the old tooth out of the serial debugging assistant
Date : 2025-12-28 Size : 3kb User : 刘虎
[VHDL-FPGA-Verilog] SerivalPC1 DL : 0: 用VHDL编写的单片机与串口的通信，通过调试，波特率为9600，在串口调试助手能看到相应的结果-Prepared with the VHDL serial communication between MCU and, through the commissioning, the baud rate is 9600, the serial debugging assistant can see the results of the corresponding
Date : 2025-12-28 Size : 589kb User : lidejjj
[VHDL-FPGA-Verilog] ps2verilog DL : 0: 本程序实现了基于FPGA的PS2键盘控制器，主机即FPGA读取键盘的键码然后解码输出到上位机（串口调试助手）显示，用户友好，调试方便，-This program implements the PS2 keyboard controller based on FPGA, the FPGA reads the keyboard master key code and then decode the output to the host computer (serial debugging assistant) shows, user-friendly and easy commissioning
Date : 2025-12-28 Size : 304kb User : 张扬
[VHDL-FPGA-Verilog] UART DL : 0: sep4020开发板uart模块的驱动程序，使用串口0，在串口调试助手上显示prochip-uart driver module development board sep4020, serial 0, serial debugging assistant prochip
Date : 2025-12-28 Size : 320kb User : 邹甬
[VHDL-FPGA-Verilog] 09_uart2 DL : 0: 串口字节收发通信，可以从PC机上通过串口调试助手输入一个字节然后从串口调试助手的接收区查找你输入的字节-Serial bytes to send and receive communication from the PC through the serial port debugging assistant enter a byte and then find your input bytes from a serial debugging assistant reception area
Date : 2025-12-28 Size : 4kb User : 李刚
[VHDL-FPGA-Verilog] verilog_uart DL : 0: verilog实现串口的调试，用串口调试助手验证通过。-verilog serial debugging and validation by serial debugging assistant.
Date : 2025-12-28 Size : 5kb User : 胡峰
[VHDL-FPGA-Verilog] uart_tx DL : 0: 在SP605开发板上实现了串口的发送程序，并且通过验证。可以通过串口调试助手进行测试！-SP605 development board serial transmission program, and validation. Tested by serial debugging assistant!
Date : 2025-12-28 Size : 248kb User : 曹荣丽
[VHDL-FPGA-Verilog] uartverilog DL : 0: FPGA串口通信，已在FPGA实验板上用串口调试助手实验成功，可以硬件实现。-FPGA serial communication experiment was a success in the FPGA board serial debugging assistant, can be implemented in hardware.
Date : 2025-12-28 Size : 40kb User : 李金伦
[VHDL-FPGA-Verilog] yibuchuanxingjiekou DL : 0: 能进行异步全双工串行通信的模块，该模块以固定的串行数据传送格式收发数据。每帧数据共10 位，其中1 位启动位，8 位数据位，1 位停止位。模块发送的数据由PC 端的串口调试助手接收，要求能发送数字和中文（一首古诗，在FPGA内采用ROM 的方式存储中文内码），并能进行切换。模块接收PC 端串口调试助手发送的16 进制数据，可按10 进制方式显示到LED 上。-Asynchronous full-duplex serial communications module can be performed, the data of the module to the fixed serial data transmission format transceiver. 10 of each frame of data, a start bit, 8 data bits, 1 stop bit. Module sends the data received from the PC side of serial debugging assistant requirements can send digital and Chinese (a poem using the FPGA code ROM stored in a manner Chinese), and can be switched. The module receives the PC side of serial debugging assistant send hexadecimal data can be decimal display on the LED.
Date : 2025-12-28 Size : 2.72mb User : 王婷
[VHDL-FPGA-Verilog] serial DL : 0: 基于FPGA的串口通讯,能够实现串口助手给fgpa发送16进制的数字，FPGA也能够向串口调试助手发送数据-Based on FPGA, serial port communication can realize serial assistant send fgpa hexadecimal Numbers, the FPGA can also send data to serial debugging assistant
Date : 2025-12-28 Size : 740kb User : wanglei
[VHDL-FPGA-Verilog] ps2 DL : 0: 使用PS2的键盘，向键盘输入字符，通过串口通讯，把字符显示到电脑上（过程需要使用到串口调试助手）-Using the PS2 keyboard to keyboard input characters via the serial port, the characters are displayed on the computer (process requires using the serial debugging assistant)
Date : 2025-12-28 Size : 11kb User :
[VHDL-FPGA-Verilog] 09_uart2 DL : 0: PC机上开串口调试助手，发送一个字符到开发板（中间通过串口线相连） FPGA收到字符后，回发给PC机上，在串口助手上显示-Open on the PC serial debugging assistant, send a character to the development board (the middle line connected through the serial port) FPGA received character, sent back to the PC, is displayed on the serial assistant
Date : 2025-12-28 Size : 604kb User : meiqiujun
[VHDL-FPGA-Verilog] uart DL : 0: 基于FPGA的UART程序设计，VERILOG HDL语言编写，可实现串口通信，波特率为115200。已通过串口调试助手验证。-FPGA-based UART program design, VERILOG HDL language, enabling serial communication baud rate to 115200. Has been verified through the serial debugging assistant.
Date : 2025-12-28 Size : 694kb User : maike cao
[VHDL-FPGA-Verilog] UART_D DL : 0: 这是一个串口调试程序，实现了数据传输判断，通过串口调试助手调试成功-This is a serial debugger, to achieve a data transfer judgments, through the serial debugging assistant debugging success
Date : 2025-12-28 Size : 394kb User : 丁强
[VHDL-FPGA-Verilog] uart DL : 0: PC机上开串口调试助手，发送一个字符到开发板（中间通过串口线相连） FPGA收到字符后，回发给PC机上，在串口助手上显示 -Open the PC serial debugging assistant, to send a character to the development board (middle connected by a serial line) After the FPGA received character is sent back to the PC, is displayed on the serial assistant
Date : 2025-12-28 Size : 1kb User : jame
[VHDL-FPGA-Verilog] new_uart DL : 0: 串口的调试程序，可用串口调试助手对串口进行收发数据的检测-Debugger serial, serial debugging assistant available to detect the serial data transceiver
Date : 2025-12-28 Size : 1.82mb User : ljp
[VHDL-FPGA-Verilog] uart_tx_rx DL : 0: 在altera的FPGA平台上实现rs232串口的自收发通信，速率为115200波特率，PC机使用串口调试助手即可观察结果。包含全部代码与工程，本人亲自测试通过。-Realization of self transmitting and receiving communication serial port of RS232 In altera on the FPGA platform, at a rate of 115200 baud rate, PC using serial debugging assistant can be observed. Contains all the code and engineering, I personally tested by.
Date : 2025-12-28 Size : 14.66mb User : 汪少锋
[VHDL-FPGA-Verilog] SDRAM DL : 0: verilog编写的SDRAM实验，有串口调试助手和相关资料-Verilog prepared by the SDRAM experiment, a serial debugging assistant and related information!!!!!!!!!!!!!!!!!!!!!
Date : 2025-12-28 Size : 11.6mb User : 网速卡
[VHDL-FPGA-Verilog] uart DL : 0: USB与pc机串口通讯的程序，开发环境为quartus11.0.该源程序是仿照黑金的教程来做的。能够往串口调试助手上顺利发文件。-Pc USB and serial port communication program development environment for quartus11.0. The source is modeled black gold tutorial to do. Serial debugging assistant can go on successfully issued a document.
Date : 2025-12-28 Size : 18.39mb User : 周燕
[VHDL-FPGA-Verilog] traffic_controller DL : 0: 一款交通灯控制芯片的verilog源码，该源码通过仿真并在FPGA上运行成功，可以实现上位机操作控制交通灯的工作模式：两相模式和四相模式。上位机操作通过串口调试助手来完成。源码中与上位机的接口采用的是UART接口。-This is a verilog code for a kind of traffic light controller. The code was simulated and verificated on FPGA. When the code works on FPGA, it can be communicated with PC using serial debugging assistant. The PC can set the mode for traffic light controller: two-phase mode or four-phase mode. In the code, the serial interface is UART.
Date : 2025-12-28 Size : 7kb User : 耿瑞

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