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[VHDL-FPGA-Verilog] sdh DL : 0: 帧同步检测源码，包括同步跟踪模块，fifo,分频模块，还有系统的测试平台-frame synchronization source detection, including synchronous tracking module, fifo, frequency module, and system test platform
Date : 2025-12-25 Size : 6kb User : liu
[VHDL-FPGA-Verilog] src DL : 0: 一个SDH中最基本传输模块STM-1的帧头检测器，verilog编程实现-A basic SDH transmission module STM-1 Header detector, verilog Programming
Date : 2025-12-25 Size : 3kb User : fredyu
[VHDL-FPGA-Verilog] d_sdhc_oct06 DL : 0: microSD卡资料.开发可以参考。 -microSD card information. development can refer to.
Date : 2025-12-25 Size : 278kb User : casual
[VHDL-FPGA-Verilog] Y312448 DL : 0: 基于VHDL的SDH专用芯片的TOP-DOWN设计，内有全套源码以及图片，内容详尽，绝对真实可靠！-VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!
Date : 2025-12-25 Size : 2.49mb User : 殷彦伟
[VHDL-FPGA-Verilog] LCAS DL : 0: 链路铜梁调整机制的实现方案，该方案是在MSTP中实现链路容量动态调整的关键技术。是基于SDH中的VCAT，在未来的传送网通信中应用广泛-Link Tongliang realize adjustment mechanism program, which is in MSTP in the link capacity is dynamically adjusted to achieve the key technology. Is based on the SDH in the VCAT, the transmission network in the next letter, a wide range of applications
Date : 2025-12-25 Size : 13kb User : 牧羊人
[VHDL-FPGA-Verilog] k21test DL : 0: 只需要FPGA两个通用管脚，就可以实现FPGA与PC机进行以太网通信！！如果你有ALTERA_DE1的开发板，可以直接下再看效果，用其他板子就要重新分配一下管脚，推荐使用电流输出。-Only two general-purpose FPGA pins, you can realize FPGA and Ethernet PC machine! ! If you have ALTERA_DE1 development board, you can look under the direct effect, with other board you will need to reconsider the distribution of pins, recommended the use of current output.
Date : 2025-12-25 Size : 860kb User : 245680
[VHDL-FPGA-Verilog] 32ET_source DL : 0: 32时隙的VHDL源代码在开发E1 2M线路的时候非常有用-32 slot of the VHDL source code in the development of E1 2M lines is very useful when
Date : 2025-12-25 Size : 1kb User : 王鹏
[VHDL-FPGA-Verilog] SDHAnalysis DL : 0: 光纤通信中的SDH数据帧解析及提取的VHDL实现源代码，共包含帧同步、E1及F1码流提取、DCC1码流提取、帧头开销串行输出四个主要模块-SDH fiber-optic communication data frame analysis and retrieval implementation of VHDL source code, include the frame synchronization, E1 and F1 stream extraction, DCC1 stream extraction, header overhead serial output four main modules
Date : 2025-12-25 Size : 31kb User : 张晓彬
[VHDL-FPGA-Verilog] rzn725SDH DL : 0: 一个关于SDH中TU-12解帧的VHDL代码-On the SDH in a solution of TU-12 frame VHDL code for
Date : 2025-12-25 Size : 1.62mb User : liyuan
[VHDL-FPGA-Verilog] vhd_SDH DL : 0: 实现从连续传输的SDH字节流中找出帧头、提取F1字节，并按照64K速率分别串行输出F1码流及时钟，其中64K时钟要求基本均匀。文件包含报告文档-SDH transmission from a continuous stream of bytes to identify header, extract F1 bytes, respectively, in accordance with 64K-rate serial output bit stream and clock F1, of which 64K clock requires a basic uniform. File contains the report of the document
Date : 2025-12-25 Size : 69kb User : ljk05
[VHDL-FPGA-Verilog] sdh1 DL : 0: 本段代码是关于SDH帧的操作的一段VHDL的代码。主要需求为两部分： 1. 从连续传输的SDH字节流中找出帧头。 2. 从SDH字节流中，提取F1字节，并按照要求输出。-This section of code is on the operation of a SDH frame VHDL code. Two main needs: 1. From the continuous transmission of SDH byte stream to find the frame header. 2. SDH bytes from the stream, extract F1 bytes and the requested output.
Date : 2025-12-25 Size : 1kb User : mao
[VHDL-FPGA-Verilog] SDH DL : 0: SDH开销的接收处理，要求： 1， A1和A2字节为帧头指示字节，A1为“11110110”，A2为“00101000”，连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机，从连续传输的SDH字节流中找出帧头。 2， E2字节为勤务话通道开销，用于公务联络语音通道，其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。（输出端口包括串行数据和64K串行时钟） -Receiving SDH overhead processing requirements: 1, A1 and A2 bytes instruction byte header, A1 is " 11110110" , A2 is " 00101000" , for three consecutive A1 bytes followed by three A2 bytes of an SDH the beginning of the frame. Asked to design a state machine, from the continuous stream of bytes in the SDH transmission header to find out. 2, E2-byte path overhead for the service, then, for the public to contact voice channels, the bit-serial rate 64KHz (8* 8K = 64). SDH byte stream request from the extraction E2 bytes, and the serial output in accordance with rates of E2 64K stream and clock, which clock requires 64K basic uniform. (Including the serial data output port and 64K serial clock)
Date : 2025-12-25 Size : 2kb User : 刘镇宇
[VHDL-FPGA-Verilog] SDH_module DL : 0: SDH帧同步头的检测，并提取其中的语音信息的模块设计-SDH frame sync detection, and extract audio information module design
Date : 2025-12-25 Size : 345kb User : 雷伟林
[VHDL-FPGA-Verilog] SDHdet DL : 0: 从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。-SDH byte stream from the extracted E2 bytes, and the serial output in accordance with rates of E2 64K stream and clock, which clock 64K basic uniform requirements.
Date : 2025-12-25 Size : 1kb User : 魏可
[VHDL-FPGA-Verilog] SDH1 DL : 0: SHD 详细设计,包含各种文档，以及VERILOG 源代码-SHD detailed design, including all documents
Date : 2025-12-25 Size : 1.7mb User : 徐强
[VHDL-FPGA-Verilog] code DL : 0: VHDL实现的LAPS协议实现的（LAPS：Link Access Procedure-SDH（SDH 上的链路接入规程））。包括发送机和接收机的程序-VHDL implementation of LAPS protocol implementation (LAPS: Link Access Procedure-SDH (SDH Link Access Procedure on)). Including procedures for transmitter and receiver
Date : 2025-12-25 Size : 5kb User : 王侃
[VHDL-FPGA-Verilog] project1source DL : 0: sdh帧同步，实现sdh帧搜索，预同步，同步，保护等各态的功能-SDH frame synchronization SDH frame search, pre-sync, synchronization, protection, the function of each state
Date : 2025-12-25 Size : 58kb User : 冷静思
[VHDL-FPGA-Verilog] VHDL_SDH DL : 0: 现代光纤通信SDH的VHDL源码，实现SDH开销的接收处理。-VHDL source code of modern fiber-optic communication SDH the SDH overhead of receiving and processing.
Date : 2025-12-25 Size : 56kb User : 张雷
[VHDL-FPGA-Verilog] SDH DL : 0: SDH vhdl实现-SDH VHDL
Date : 2025-12-25 Size : 171kb User : real