Search - Rectangle

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[VHDL-FPGA-Verilog] rectangle DL : 0: 在屏幕上形成矩形的VHDL程序，感觉还可以。-Rectangle on the screen at the formation of the VHDL process can also be felt.
Date : 2025-12-16 Size : 184kb User : 肖
[VHDL-FPGA-Verilog] verilogvga DL : 0: 基于spartan3e的vga程序，测试通过，在屏幕上显示大小矩形-Based on the vga spartan3e procedures, tests passed, the size of the rectangle on the screen
Date : 2025-12-16 Size : 256kb User : zhangjian
[VHDL-FPGA-Verilog] A_digital_WaveformGenerator_and_Oscilloscope_based DL : 0: 一种基于BASYS开发板(Xilinx Spartan-3E FPGA)的波形发生器和示波器的设计，可以产生多种可调波形，并实时显示在电脑显示器或者投影仪上。波形发生器采用基于ROM的数字控制振荡器（NCO）实现，示波器采用VGA接口实时显示。-A kind of digital WaveGenerator and Oscilloscope based on tne BASYS experiment board which has a Xilinx Spartan-3E FPGA on it.This design can make adjustable sine,triangle and rectangle waveform.It also can show the waveform real time on a computer dispaly or a projecting apparatus via a VGA cable.The emphases of this project is to realize real-time VGA interface in a FPGA.
Date : 2025-12-16 Size : 3.26mb User : 张文
[VHDL-FPGA-Verilog] verilog-vga DL : 0: Verilgo编写的VGA显示接口示例程序, 在显示器上显示矩形彩条, 包含Quartus II 8.1工程文件及VGA的相当资料(PDF及WORD文档)-Verilgo prepared VGA display interface sample program, the color of the rectangle on the display, including the Quartus II 8.1 project file and VGA considerable data (PDF and WORD document)
Date : 2025-12-16 Size : 1.69mb User : Joseph
[VHDL-FPGA-Verilog] VGA_PS2 DL : 0: 使用键盘控制显示器上矩形框的移动。使用verilog HDL编写。已经在spartan3-E开发板上实现。保证好用。-Use the keyboard to control the movement of the display rectangle. Prepared using verilog HDL. Has been achieved spartan3-E on the development board. To ensure ease of use.
Date : 2025-12-16 Size : 1.7mb User : zhangwei
[VHDL-FPGA-Verilog] Rendering_primitives DL : 0: Some 2D graphic rendering in VHDL: - Line - Draw a line - Circle - Draw circle - BitBLT - Draw a rectangle - Sine and cosinus lookup tables - Rotation - Rotate line
Date : 2025-12-16 Size : 13kb User : lance_corona
[VHDL-FPGA-Verilog] dd DL : 0: 本系统由FPGA构建，使用Nexys2（120万门）开发板。在VGA接口显示器上绘制图形，分辨率1024x768，绘图部分基于硬件，有画点、画线、画矩形、字符功能。使用32位处理器产生使用应绘制的内容，使用PSRAM作为显示存储器。可以以很高的刷新率绘制各种图形，具有很高的应用价值。-The system built by the FPGA of Nexys2 (120 million gates) development board. VGA connector on the monitor to draw graphics, 1024x768 portion of the drawing is based on the hardware, draw point, draw lines, draw a rectangle, the character function. As the display memory 32 of processor use should be drawn, using PSRAM. A variety of graphics can be drawn with a high refresh rate, has a high value.
Date : 2025-12-16 Size : 57kb User : wen
[VHDL-FPGA-Verilog] BasysRevEBist DL : 0: basys板描述介绍信号发生器在科研以及生产实践领域有着广泛的应用。传统的信号发生器通常是通过模拟电路的振荡、变换得到各种信号。由于模拟器件以及模拟电路自身的局限性，其发展已经遇到了瓶颈。直接数字- kind of digital WaveGenerator and Oscilloscope based on tne BASYS experiment board which has a Xilinx Spartan-3E FPGA on it.This design can make adjustable sine,triangle and rectangle waveform.It also can show the waveform real time on a computer dispaly or a projecting apparatus via
Date : 2025-12-16 Size : 1.19mb User : 赵志彪
[VHDL-FPGA-Verilog] verilogvga DL : 0: 这是FPGA用Verilog写的VGA显示程序。可以显示一个矩形框和一个小矩形。-This is the FPGA using Verilog VGA display program. You can display a rectangular box and a small rectangle.
Date : 2025-12-16 Size : 235kb User : 胡刚
[VHDL-FPGA-Verilog] vga DL : 0: 该工程设计需要在VGA 显示器上显示背景为蓝色，中央显示一个绿色的边框和一个粉色的矩形-The project design requires a VGA monitor to display a blue background, the central display a green border and a pink rectangle
Date : 2025-12-16 Size : 1kb User : 王世豪
[VHDL-FPGA-Verilog] vga_dis DL : 0: 该代码设计在VGA显示器上显示背景蓝色，中央绿色边框和粉色矩形。-The code is designed to display on a VGA monitor background blue, central green border and pink rectangle.
Date : 2025-12-16 Size : 2kb User : cuixiao
[VHDL-FPGA-Verilog] VGA_caidai_zifu_juxing DL : 0: verilog实现VGA显示的代码，包括驱动，时钟管理，显示的全部，代码中包括三个实例，一个最常见的八个彩带型，一个矩形框，一个魔幻彩带显示实现，全部代码实现。-verilog implementation code VGA display, including the driver, clock management, all of the code displayed include three instances, one of the most common type of eight ribbons, a rectangle, a magic show ribbon achieve all code.
Date : 2025-12-16 Size : 1.09mb User : 贾俊超