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[VHDL-FPGA-Verilog] 引爆器 DL : 0: 数字密码引爆器的输入描述：1、在开始输入密码以前的等待状态，首先要按READY键，表示目前准备就绪，可以输入数字密码；2、当引爆事件发生后，应该回到等待状态，设置WAIT_T键；3、如果输入密码不正确，此时要操作READY和WAIT_T是不起作用的，必须由设计人员重新设置到等待状态，设置SETUP键，SETUP为内部按键，操作人员应该不能接触；4、确定密码输入后，要设计一个点火按键FIRE；-digit passwords detonated's input Description : one at the start and enter the password before the wait state, according to First READY button, now ready to be imported into digital code; Two, when detonated after the incident, should wait for the state to set up WAIT_T bond; three, if a password is not correct, this time to operate READY WAIT_T and is non-functional, the design must be re-installed to wait for the state, set up SETUP button SETUP internal keys, the operator should not contact; 4 to determine the password, to design a FIRE- ignition keys;
Date : 2026-01-02 Size : 24kb User : 刘卫
[VHDL-FPGA-Verilog] ELEC_LOCK DL : 0: 4位电子密码锁，带键盘扫描、按键防抖动、LCD驱动编译码-four electronic password lock with a keyboard scan button shake, LCD driver encryption
Date : 2026-01-02 Size : 2kb User : xf
[VHDL-FPGA-Verilog] reg_comp DL : 0: 4X4 KEYPAD 的密码比较模块，可以核对6位的密码-4x4 KEYPAD password comparison module, can check the password 6
Date : 2026-01-02 Size : 136kb User : 分第三
[VHDL-FPGA-Verilog] 123zsfsafdsafds DL : 0: 里面有一个很实用的源码,数字引爆密码设计-there is a very practical source, digital design detonated Password
Date : 2026-01-02 Size : 14kb User : 周昭珍
[VHDL-FPGA-Verilog] cla_vhd DL : 0: 超前进位加法器的例子,包括源码和测试文件,压缩包,无密码.-CLA of examples, including source code and test documents, compressed, without a password.
Date : 2026-01-02 Size : 1kb User : 王卫
[VHDL-FPGA-Verilog] BBSdfbdgdr DL : 0: 如果遇到MD5加密文件，而又不知道密码的，请在数据库中换上这组加密的数据吧 16位：7a57a5a743894a0e 32位：21232f297a57a5a743894a0e4a801fc3 那么密码就是admin-if they MD5 encryption, and do not know the password. please database with a group of encrypted data it 16 : 7a57a5a743894a0e 32 : 21232f297a57a5a743894a0e4a801fc3 password is then ad min
Date : 2026-01-02 Size : 3.8mb User : 西西公主
[VHDL-FPGA-Verilog] counter16 DL : 0: 风格非常好一六位计数器无密码质量很高-style very good counter-16 high quality Password
Date : 2026-01-02 Size : 83kb User : zt
[VHDL-FPGA-Verilog] vhdl_example DL : 0: 一些vhdl的简单例子。直接解压，不用密码。-instantiate some simple examples. Direct unpack, without a password.
Date : 2026-01-02 Size : 15kb User : 计量
[VHDL-FPGA-Verilog] sdr_c_trl_verilog DL : 0: SDRAM 控制器的Verilog代码经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
Date : 2026-01-02 Size : 12kb User : 曹大壮
[VHDL-FPGA-Verilog] mimasuo2S50 DL : 0: 8位密码锁的实现，初始状态默认为密码正确，密码输入正确方可设密码，以后必须按对密码才可重设-8 password lock the realization of initial state defaults to the correct password, the password can input the correct password. After the password must be re-established before
Date : 2026-01-02 Size : 497kb User : jerry
[VHDL-FPGA-Verilog] password_lock DL : 0: 电子密码锁，采用基于fpga的设计，可以设置6位密码-Electronic code locks, FPGA-based design, can be set 6 password
Date : 2026-01-02 Size : 1.36mb User : xjl
[VHDL-FPGA-Verilog] VHDL-topics-Electronic-locks DL : 0: VHDL密码锁设计专题，学习使用VHDL设计密码锁-VHDL design of the password lock feature and learning to use the VHDL design code lock
Date : 2026-01-02 Size : 151kb User : 蔡宇佳
[VHDL-FPGA-Verilog] password DL : 0: 完成开锁、超时报警、超次锁定、管理员解密、修改用户密码基本的密码锁的功能-Completion of lock, time out alarm, lock and Ultra, the administrator decrypt, modify the user password lock function of the basic
Date : 2026-01-02 Size : 777kb User : rokin_lv
[VHDL-FPGA-Verilog] lock-and-lcd DL : 0: 基于博创实验箱UP-CUP-FPGA2C35-Ⅱ和Verilog HDL硬件描述语言，分为按键输入模块、LED指示灯模块及LCD显示模块，采用按键BTN1、BTN2作为输入端输入四位密码与事先设定的密码进行匹配，由D1、D2、D3、D4四盏LED灯来指示输入密码的位数。开机时，LCD显示“HELLO! WELCOME!Enter the code:当”，密码输入正确时，LED灯D7亮，同时在实验箱LCD显示屏上显示字符串“Good! Well done!you are right!!!”，当密码输入错误时，LED灯D8亮，并在LCD显示屏上显示字符串“NO!!You stupid!!you are worry!!!”其中，LCD显示作为本次设计的核心内容，字符型LCD通常有14条引脚线或16条引脚线的LCD，多出来的2条线是背光电源线VCC(15脚)和地线GND(16脚)，其控制原理与14脚的LCD完全一样-Base YuBo gen experiment box UP- FPGA2C35- Ⅱ and director- Verilog HDL hardware description language, divided into key input module, the LED indicator light module and LCD display module, the BTN1, BTN2 buttons as input the input password and set in four matches, the password by D1, D2 and D3, D4 four lamp that LED lamp to indicate input password of digits. Boot, LCD display "HELLO!!!!!!!!!! The code: backgound Enter when", a password when right, LED lamp, while D7 light displayed on the LCD screen experiment box string "Good!! Well done! You right!!!" hero When a password mistake, LED lamp light, and in D8 displayed on the LCD screen "NO!! You string can be hindered stupid!!!!!!!!!!!!!!!!!" hero Among them, LCD display as the core content of the design, character type LCD usually has 14 pin line or 16 pins line of LCD, extra 2 line is backlit cord VCC (15 feet) and landlines GND (16 feet), the control principle and 14 feet LCD exactly the same
Date : 2026-01-02 Size : 3kb User : 吴寿武
[VHDL-FPGA-Verilog] password DL : 0: verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。-verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.
Date : 2026-01-02 Size : 565kb User : 陈振睿
[VHDL-FPGA-Verilog] password-locker DL : 0: 简单的单号密码锁程序在verilog上实现包括测试程序-simple password locker programme based on verilog, which including test bench
Date : 2026-01-02 Size : 1kb User : 贺铮
[VHDL-FPGA-Verilog] password DL : 0: password vhdl代码用于basys2板子-password for basys SJTU STUDENTS
Date : 2026-01-02 Size : 2kb User : 周晓辰
[VHDL-FPGA-Verilog] verilog--password-lock DL : 0: 基于ＦＰＧＡ的密码锁　 verilog- verilog FPGA password lock
Date : 2026-01-02 Size : 2kb User : 万中原
[VHDL-FPGA-Verilog] Digital-Password-Lock DL : 0: 数字密码锁具体要求如下： 1. 系统密码设置使用拨位开关sw[7:0]，限定为4位密码；sw[7:6]、sw[5:4]、sw[3:2]、sw[1:0]分别对应从左到右密码的第1、2、3、4位；每一位的取值范围限定在0、1、2三个数中。 2. 用btn[2:0]作为输入键，btn[0]、btn[1]、btn[2]分别对应的有效输入为十进制数0、1、2（由于btn数有限，系统不支持解锁含有数字3的密码）。 3. 输入的密码显示在7段数码显示管对应位上，顺序为从左至右，未输入密码时数码管不显示数字，只有对应位输入密码后数码管才点亮。 4. 输入密码与预存密码相同时，开锁成功，LED灯ld[7]亮起；否则开锁失败，ld[0]亮起。 5. 具有一个复位按键btn[3]。按键后，回到初始状态。 -Digital lock specific requirements are as follows: 1. The system password is set using DIP switches sw [7: 0], is limited to four passwords sw [7: 6], sw [5: 4], sw [3: 2], sw [1: 0], respectively left to right 1,2,3,4 digit password every one of the range is limited to three numbers 0,1,2. 2. Use btn [2: 0] as input keys, btn [0], btn [1], btn [2] corresponding to each active input as a decimal number 0,1,2 (due to the limited number btn, the system does not support the unlock 3 containing numeric password). 3. Enter the password displayed on the 7-segment display tubes corresponding bit on, the order left to right, did not enter a password when no digital display numbers, enter the password only after the corresponding bit digital tube was lit. 4. Enter the same password stored password, unlock success, LED lights ld [7] is lit otherwise the lock fails, ld [0] is illuminated. 5. With a reset button btn [3]. After the keys back to the initial state.
Date : 2026-01-02 Size : 5kb User : 刘东辉
[VHDL-FPGA-Verilog] Password lock DL : 0: 一个 Quartus II 工程，芯片为EP3C55F484C8，是一个简单的保险箱密码锁。包含分频器、键盘去抖、8选1选择器、扬声器模块、动态扫描模块等多个模块。主要功能： 1. 保险箱上设有密码输入和钥匙锁双重保险。 2. 当密码输入正确后，左边的指示灯亮，此时插入钥匙即可打开保险箱；当密码输入错误后，右边的指示灯亮，发出报警信号，此时需要重新输入密码。 3. 保险箱的密码可根据需要随时更换。(A Quartus II project, the chip is EP3C55F484C8, is a simple safe lock. It includes frequency divider, keyboard shake, 8 selector 1 selector, loudspeaker module, dynamic scanning module and so on. Main functions: 1. the safety box is provided with double insurance of password input and key lock. 2. when the password is correct, the indicator on the left is bright. At this time the key can be opened to open the safe. When the password is wrong, the indicator on the right is bright and the alarm signal is sent. The password is reentered at this time. 3. the cipher's password can be changed at any time.)
Date : 2026-01-02 Size : 4.56mb User : yves05

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