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[VHDL-FPGA-Verilog] pipe DL : 0: verilog编写的流水线模块-Verilog modules prepared by the Pipeline
Date : 2025-12-24 Size : 5kb User : 刘陆陆
[VHDL-FPGA-Verilog] add_16_pipe DL : 0: 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Date : 2025-12-24 Size : 1kb User : qjyong
[VHDL-FPGA-Verilog] vhdl_i2c DL : 0: 7． IIC 接口EEPROM 存取实验按动开发板键盘某个键CPLD 将拨码开关的数据写入EEPROM 的某个地址，按动另外一个键，将刚写入的数据读回CPLD，并在数码管上显示。帮助读者掌握I2C 的总线协议和EEPROM 的读写方法。-7. IIC EEPROM Access Interface Development Board experimental pressed a button keyboard CPLD code will go into the data switch E EPROM a certain address, pressed another button, just write the data back to reading CPLD, and the digital pipe show. To help readers master the I2C bus protocol and EEPROM read and write methods.
Date : 2025-12-24 Size : 410kb User : 赵海东
[VHDL-FPGA-Verilog] work3CNT4BDECL7S DL : 0: 7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
Date : 2025-12-24 Size : 81kb User : lkiwood
[VHDL-FPGA-Verilog] 4x4Key_daisy090708 DL : 0: 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现对4x4键盘的输入控制，并显示在一个8段式数码管上。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 the development board to realize 4x4 keyboard input control, and displayed in an eight-stage digital pipe.
Date : 2025-12-24 Size : 446kb User : Daisy
[VHDL-FPGA-Verilog] 7seg-led DL : 0: VHDL的彩灯程序，内含数码管和led灯的显示，按照各种循环方式一次显示-The Lantern VHDL program, containing the digital pipe and led lights are displayed, according to a variety of recycling methods show once again that
Date : 2025-12-24 Size : 17kb User : liwx
[VHDL-FPGA-Verilog] frequency_meter DL : 0: 简易频率计，能够测试0~10000KHz之间的脉冲信号频率，并显示在数码管上。利用了100KHz的脉冲作为基准信号。包含课程设计报告。-Simple frequency meter, to test pulses between 0 ~ 10000KHz signal frequency and displays in the digital pipe. Use 100KHz pulse as a reference signal. Includes curriculum design report.
Date : 2025-12-24 Size : 12kb User : 石帆
[VHDL-FPGA-Verilog] i2c DL : 0: 按动开发板键盘某个键CPLD将拨码开关的数据写入EEPROM的某个地址，按动另外一个键，将刚写入的数据 -- 读回CPLD，并在数码管上显-Pressing a button keyboard CPLD development board DIP switches, the data will be written to EEPROM in an address, pressing another key, the newly written data- read back CPLD, and significant in the digital pipe
Date : 2025-12-24 Size : 3kb User : rongchao
[VHDL-FPGA-Verilog] wodewenjian DL : 0: 基于FPGA的电梯控制系统的设计将电梯的运行状态划分为开门，一层，二层，三层，四层五个状态，设一层开门为电梯的初始状态，up1,up2,up3分别作为一层，二层，三层的上升请求，四层没有上升请求；down2,down3,down4分别作为二层，三层，四层的下降请求，同理一层是没有下降请求的；s1,s2,s3,s4分别作为一层，二层，三层，四层的停站请求；x1,x2,x3,x4分别作为一层，二层，三层，四层的停站请求显示；door作为门的状态，“0”表示关，“1”表示开；mode作为电梯的运行模式，这里可以用一个seg模块将楼层的显示转换为数码管显示。 -The elevator control system based on FPGA design Will lift operation into a layer, the second door, and three layers, four layers, one of five layers of the elevator opened for the initial state, respectively, up2 up3 up1, as a layer 2 and layer 3, the rise and rise no request for four layers, Down2 down3 down4, respectively, as a second, third, fourth floor request, a drop down the request is not, S1, s2, s3, respectively, as a layer s4 2, 3, 4 stops, Clamps its x1, x2, respectively, as a x4 x3 layer 2 and layer 3, 4, stop that request, As the door, held "0", "1" say, Mode of operation mode, as the elevator here can use a seg module will be converted to digital display floor pipe display.
Date : 2025-12-24 Size : 1kb User : 吴海霞
[VHDL-FPGA-Verilog] edapinluji DL : 0: 接通电源，可以测输入的频率，显示在数码管上。-Switch on the power, you can measure the input frequency, displayed on the digital pipe.
Date : 2025-12-24 Size : 5kb User : lovesoph
[VHDL-FPGA-Verilog] temperature DL : 0: 使用FPGA控制18B20达到温度采集过程，并显示在数码管上。-Achieved using the FPGA control 18B20 temperature acquisition process and display the digital pipe.
Date : 2025-12-24 Size : 2kb User : 彭杨
[VHDL-FPGA-Verilog] ee DL : 0: 一个七段解码器模块，c2～c0是解码器的3个输入，当输入值不同时，输出不同的字符。如表中所示，当输入值为100～111时，输出空格，即数码管全暗。七段数码管的不同段位用数字0～6表示，注意七段数码管是共阳极的，即各管段输入低电平时，数码管亮；否则数码管暗。 -A seven-segment decoder module, c2 ~ c0 is a 3 input decoder, when the input value is not the same time, the output of different characters. As the table shows, when the input is 100 to 111, the output space, that is, the digital control and dark. Dan seven-segment digital tube with different numbers 0 to 6, said attention is the common anode seven-segment digital tube, that the pipe input low, the digital tube light or digital control dark.
Date : 2025-12-24 Size : 2kb User : 潘小丽
[VHDL-FPGA-Verilog] FPGA-verilog DL : 0: 用Verilog语言编写的一些简单的FPGA入门实验，用ALTERA DE2开发板和Quartus_II软件开发环境。包括：流水灯实验、数码管显示实验-With Verilog language preparation some simple introduction experiment, with FPGA ALTERA DE2 development board and Quartus_II software development environment. Include water lamp experiment, digital pipe display experimentation, etc
Date : 2025-12-24 Size : 10kb User : 星光依旧
[VHDL-FPGA-Verilog] seg71 DL : 0: ７段数码管测试实验１：以动态扫描方式在８位数码管“同时”显示０--7 实验的目的是向用户介绍多个数码管动态显示的方法。动态显示的方法是，按一定的频率轮流向各个数码管的COM端送出低电平，同时送出对应的数据给各段。-7-segment test experiment 1: 8-bit dynamic digital scanning mode in the pipe " while" display 0- 7 experiment is introduced to the user multiple digital dynamic display method. Dynamic display method is to rotate at a certain frequency of the various digital control of the COM to send low end, while the corresponding data sent to each segment.
Date : 2025-12-24 Size : 1kb User : zhangqiang
[VHDL-FPGA-Verilog] seg71 DL : 0: ７段数码管测试实验１：以动态扫描方式在８位数码管“同时”显示０--7 实验的目的是向用户介绍多个数码管动态显示的方法。动态显示的方法是，按一定的频率轮流向各个数码管的COM端送出低电平，同时送出对应的数据给各段。-7-segment test experiment 1: 8-bit dynamic digital scanning mode in the pipe " while" display 0- 7 experiment is introduced to the user multiple digital dynamic display method. Dynamic display method is to rotate at a certain frequency of the various digital control of the COM to send low end, while the corresponding data sent to each segment.
Date : 2025-12-24 Size : 1kb User : riversky
[VHDL-FPGA-Verilog] digicnt DL : 0: 带全局复位的1小时倒数计时器。显示在4个7段译码管上，使用48MHz晶振驱动。-1 hour with the global reset countdown timer. 4 7-segment display decoder in the pipe, using 48MHz crystal driver.
Date : 2025-12-24 Size : 377kb User : 夏江南
[VHDL-FPGA-Verilog] seg7led DL : 0: quartus 2七段管的html语言实现-quartus 2 html language seven sections of pipe
Date : 2025-12-24 Size : 1kb User : 陈涛
[VHDL-FPGA-Verilog] clk DL : 0: 这是一个数字秒表的设计。几时周期为0.01s-1h。带有计数器的清零端，还有一个秒表的计时起止控制开关，最后计时信息显示在数码管上。-This is a digital stopwatch design. When a period of 0.01s-1h. Cleared with the end of the counter, and a stopwatch start and end time-control switch, the last time the information displayed on the digital pipe.
Date : 2025-12-24 Size : 1kb User : linpy
[VHDL-FPGA-Verilog] pipe DL : 0: pipe lining.It is based on multiple pipe lining.Pipe lining concept utilized in processors.
Date : 2025-12-24 Size : 1kb User : kiran dash
[VHDL-FPGA-Verilog] pipe25_rc5 DL : 0: pipe可以用于绘制随机petri网和系统性能分析(pipe for help leaner in start stage get more about how to conduct petri net)
Date : 2025-12-24 Size : 1.97mb User : tiashiaimeili

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