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[VHDL-FPGA-Verilog] uart_verilog DL : 0: 包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
Date : 2025-12-16 Size : 9kb User : 施向东
[VHDL-FPGA-Verilog] 国外的VHDL应用例子 DL : 0: 国外的VHDL应用例子，大家可一好好参考一下！-abroad VHDL Application examples, we can make reference to a properly!
Date : 2025-12-16 Size : 227kb User : gjd
[VHDL-FPGA-Verilog] sorce DL : 0: 一个很好的利用verilog编程实现的cpu程序，一定要好好利用。-a good use of the Verilog Programming cpu procedures, we must make good use of.
Date : 2025-12-16 Size : 6kb User : 刘永
[VHDL-FPGA-Verilog] richic_vga_top DL : 0: 有关 VHDL进行VGA显示的源程序，请大家好好参考-VHDL for the VGA display the source code, please make reference to
Date : 2025-12-16 Size : 27kb User : 111
[VHDL-FPGA-Verilog] VERILOGBLOCK DL : 0: 在blocking 模块中按如下写法，仿真与综合的结果会有什么样的变化？作出仿真波形，分析综合结果。 -in blocking module by the following wording, simulation and synthesis of the results will be what kind of changes? Make simulation waveform analysis and comprehensive results.
Date : 2025-12-16 Size : 9kb User : 周正华
[VHDL-FPGA-Verilog] div DL : 0: div的verilog开发程序，做稍微修改就可以应用到具体的工程当中-div of Verilog development process, make a slight modification can be applied to specific projects which
Date : 2025-12-16 Size : 164kb User : 杨华
[VHDL-FPGA-Verilog] sin DL : 0: sin產生器，可以於VHDL產生sin之數值波形，進而輸出至dac做轉換-sin generator can produce sin in VHDL of the numerical waveform, and then make the conversion output to dac
Date : 2025-12-16 Size : 1.03mb User : lin
[VHDL-FPGA-Verilog] pcm1804_i2s_data_adjust2 DL : 0: 用于pcm1804调整I2S的数据，使I2S的音频同步并且在FIFO中不溢出。能够自动判断FIFO --中的状态，通过调整从FIFO中输出的数据的个数来使FIFO既不上溢也不下溢。 -- 为了达到更高的精度要求，可以通过加大采样时钟clk的频率。-I2S for pcm1804 adjusted data, so that I2S audio synchronization and FIFO does not overflow. Can automatically determine the FIFO- the state, by adjusting the output from the FIFO in the number of data in order to make the FIFO does not overflow or underflow.- In order to achieve higher precision, you can increase the sampling clock frequency of clk.
Date : 2025-12-16 Size : 2kb User : WQL
[VHDL-FPGA-Verilog] VHDL DL : 0: 源代码不同软件对VHDL语法的支持范围是不一样的,以下程序中的某些语句可能不能运行在所有的软件平台之上,因此程序可能要作一些修改,同时务必注意阅读程序中的注释。-Source code for different types of software support for VHDL grammar is not the same as the scope, the following procedures for some of the statements may not be able to run on all of the software platform, so the procedures may have to make some changes, but be sure to pay attention to the footnote reading program.
Date : 2025-12-16 Size : 637kb User :
[VHDL-FPGA-Verilog] dianzi_vhdl DL : 0: 高等电子技术的EDA部分，内部还有一个dds的vhdl代码，我参考该代码，实现了10位和8位的dds，在EPF10K10TC144-4芯片验证通过。-Advanced electronic technology EDA part of a dds within the VHDL code, I make reference to the code, achieved a 10 and 8 of the dds, in EPF10K10TC144-4 chip verification through.
Date : 2025-12-16 Size : 183kb User : eroad
[VHDL-FPGA-Verilog] VoteMa DL : 0: 投票器。这个好像是3人投票器，可以用来做5人的吧~也是以前我们实验的时候用过的。仿真和下载都很顺利。-The voting device. This seems to be 3 people to vote, and can be used to make 5 of it ~ is also the past, we used the experimental time. Simulation and downloading has gone smoothly.
Date : 2025-12-16 Size : 67kb User : catalina
[VHDL-FPGA-Verilog] div_js DL : 0: 技术分频器。把时钟分为奇数个，好像我做出来是个通用的。-Technology divider. The clock is divided into odd-numbered months, as I make out is a common.
Date : 2025-12-16 Size : 266kb User : catalina
[VHDL-FPGA-Verilog] FullAdder_4 DL : 0: 这是一个4位全加器，用一个1位半价做的一位全加，然后做成的四位半加。-This is a 4-bit full adder, a half-price with a make a full-adder, and then made four half adder.
Date : 2025-12-16 Size : 95kb User : catalina
[VHDL-FPGA-Verilog] seg7_1a DL : 0: 输入一个四位二进制数，使用拨码开关表示，使发光二极管显示这四位二进制数。-4 Enter a binary number, use the dial code switches that make light-emitting diodes show the four binary number.
Date : 2025-12-16 Size : 202kb User : fishafish
[VHDL-FPGA-Verilog] QUARTUSII-FPGA DL : 0: 使用QUARTUS做FPGA开发全流程，适用于初学者-Quartus FPGA development make use of the entire flow for beginners
Date : 2025-12-16 Size : 1.27mb User : s.y
[VHDL-FPGA-Verilog] PLDszzds DL : 0: VHDL的试验教程，可以用来做试验。写的很不错，如果想写点东西，可以参考。-VHDL Test Guide can be used to make the pilot. Write very well, if you want to write something, you can reference.
Date : 2025-12-16 Size : 467kb User : chengpan
[VHDL-FPGA-Verilog] yw DL : 0: 自己编的走马灯程序用了就知道太好使了真的-Own procedures for the lantern will know very well spent to make a really
Date : 2025-12-16 Size : 254kb User : 付长洲
[VHDL-FPGA-Verilog] alarm DL : 0: 1．6个数码管动态扫描显示驱动 2．按键模式选择(时\分\秒)与调整控制 3．用硬件描述语言(或混合原理图)设计时、分、秒计数器模块、按键控制状态机模块、动态扫描显示驱动模块、顶层模块。要求有闹钟定闹功能，时、分定闹即可，无需时、分、秒定闹。要求使用实验箱左下角的6个动态数码管(DS6 A~DS1A)显示时、分、秒；要求模式按键和调整按键信号都取自经过防抖处理后的按键跳线插孔。-1.6 Digital control of dynamic scanning display driver 2. Mode selection button (when minutes and seconds) and adjust the control 3. Using hardware description language (or a combination of schematic diagram) design, minute and second counter module, key control state machine module, dynamic scanning display driver module, the top-level module. Required to make the alarm set function, the sub-set can make without hour, minute, second set downtown. Require the use of lower-left corner of the experimental box 6 dynamic digital tube (DS6 A ~ DS1A) shows hours, minutes, seconds request mode button and adjust the signal from the button after button after the Anti-shake deal with jack jumper.
Date : 2025-12-16 Size : 607kb User : xulina
[VHDL-FPGA-Verilog] Lab1_FPGA DL : 0: lab1——FPGA这个文件中体统了如何如何使用verilog Hdl以及如何使其在FPGA开发板上实现-lab1- FPGA decency in this document on how to how to use the verilog Hdl and how to make it realize in FPGA development board
Date : 2025-12-16 Size : 143kb User : 陈轩辕
[VHDL-FPGA-Verilog] use-AUTHERWARE-to-make-LED-display DL : 0: 用AUTHERWARE制作体育馆大屏幕的方法与技巧-use AUTHERWARE software to make LED display
Date : 2025-12-16 Size : 32kb User : xujiajun

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