Search - MATLAB c

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[VHDL-FPGA-Verilog] qqq DL : 0: 数字滤波器的vhdl源代码.在quartus上运行过,里面还有matlab的仿真文件.-Digital filter of the VHDL source code. In Quartus run-off, along with the simulation matlab file.
Date : 2025-12-27 Size : 26kb User : 萧勇
[VHDL-FPGA-Verilog] c2812rtdxtest_c2000_rtw DL : 0: 由MATLAB生成的RTDX的源代码，由模型搭建，然后自动生成DSP的源代码-RTDX generated by MATLAB source code, set up by the model, and then automatically generate DSP source code
Date : 2025-12-27 Size : 93kb User : sun
[VHDL-FPGA-Verilog] fftw3mat DL : 0: 介绍了如何利用c语言来实现数字信号处理中常用的fft，并介绍了如何利用matlab验证-intruduce how to use c to finish fft,and use matlba to ensure
Date : 2025-12-27 Size : 862kb User : 黄易飞
[VHDL-FPGA-Verilog] tdoa123 DL : 0: Position location services will not only provide new customer options and products for wireless carriers, but will also provide features that could dierentiate services in dierent markets (i.e., dierentiation between PCS, cellular, and specialized mobile radio) [4]. Location systems will also provide wireless carriers and vendors who use position location the ability to charge for service based on location, within a particular cell site, or in a speci c location such as an oce, home, or car. This will allow wireless service providers to control customer usage by oering cost incentives that match service plans for the wireless infrastructure and networking resources.
Date : 2025-12-27 Size : 810kb User : vijay
[VHDL-FPGA-Verilog] SOU DL : 0: 这是用C写的正弦函数定点数据生成代码，内容是生成verilog中RAM或者ROM和Matlab处理时的所用的数据。-It is written with C fixed-point data generate code sine function, the content is generated verilog RAM or ROM, and Matlab in the processing of the data used.
Date : 2025-12-27 Size : 1kb User : wolly
[VHDL-FPGA-Verilog] pskdem_fixed DL : 0: psk解调的定点仿真模型。另外DEC2HEX.C负责将十进制的数据文件转换为十六进制的数据文件，因为MATLAB输出数据格式为十进制，而NC-VERILOG能够读取的数据格式为十六进制，所以需要转换。-psk demodulation of the fixed-point simulation models. In addition DEC2HEX.C responsible for the data file is converted to decimal hex data file, as MATLAB output data format is decimal, and NC-VERILOG can read the data in hexadecimal format, you need to convert.
Date : 2025-12-27 Size : 11kb User : 杨芳
[VHDL-FPGA-Verilog] rom--mif DL : 0: 生成fpga的rom查找表的c语言和matlab程序还有一个生成正弦和余弦mif文件的生成器-fpga rom lut
Date : 2025-12-27 Size : 131kb User : liuheshan
[VHDL-FPGA-Verilog] 232315digitalPLL DL : 0: vhdl matlab ...............simulink c++........ probgramme
Date : 2025-12-27 Size : 2kb User : said
[VHDL-FPGA-Verilog] testcordic DL : 0: catapult c cordic程序，可以转换成verilog语言，完成用modelsim进行仿真，结果可以与matlab进行比较。-catapult c cordic program
Date : 2025-12-27 Size : 514kb User : wangjun