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[VHDL-FPGA-Verilog] 自适应滤波算法（LMS）和kalman滤波算法 DL : 0: 自适应滤波算法（LMS）和kalman滤波算法
Date : 2009-05-18 Size : 1.29kb User : sunyu85@gmail.com
[VHDL-FPGA-Verilog] lms verilog DL : 1: lms veriog程序，不错的代码
Date : 2012-01-11 Size : 946byte User : pofet@sina.com
[VHDL-FPGA-Verilog] FPGA_LMS DL : 1: VHDL写的LMS算法程序。利用本地正弦信号，根据LMS算法对输入信号进行跟踪。用以产生和输入信号同频同相的本地信号。-VHDL LMS algorithm written procedures. The use of local sinusoidal signal, according to the LMS algorithm for tracking the input signal. Used to produce and the input signal with frequency phase with the local signal.
Date : 2026-01-10 Size : 264kb User : 黄鹤
[VHDL-FPGA-Verilog] fir6dlms DL : 1: lms的verilog代码，我找了好久在才找的的，好东西，大家一起学习-LMS of the Verilog code, I am looking for a long time before looking at the good things we can work together to learn
Date : 2026-01-10 Size : 1kb User : 李允
[VHDL-FPGA-Verilog] ante DL : 0: 智能天线自适应LMS算法，假设具有4个天线阵元。-Smart antenna adaptive LMS algorithm, the assumption that with four million antenna array.
Date : 2026-01-10 Size : 4kb User : 黄虎
[VHDL-FPGA-Verilog] adaptive_lms_equalizer_latest.tar DL : 0: In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random. To handle this, multipath affected channels require Equalizers at receaver end. such equalizer uses different learning Algorithms for identifying channels continuously. This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.
Date : 2026-01-10 Size : 14kb User : Arun
[VHDL-FPGA-Verilog] AdaptiveLMSequalizer DL : 0: 通信中的用的LMS均衡算法VHDL实现，代码不长，很容易看懂-Communication with the LMS equalization algorithm to achieve VHDL code is not long, it is easy to understand
Date : 2026-01-10 Size : 3kb User : 王王
[VHDL-FPGA-Verilog] lms DL : 0: 一个不错的关于lms算法的verilog代码，算然只有两级，但是对了解lms用HDL描述有很好的理解作用。希望对大家有用~-A good lms algorithm on the verilog code, development environment, I can not find, even if the vhdl it! We hope to be useful
Date : 2026-01-10 Size : 1kb User : onion
[VHDL-FPGA-Verilog] fir_lms DL : 0: 一个不错的关于lms算法的verilog代码，算然只有两级，但是对了解lms用HDL描述有很好的理解作用。希望对大家有用~-A good lms algorithm on the verilog code, development environment, I can not find, even if the vhdl it! We hope to be useful
Date : 2026-01-10 Size : 1kb User : onion
[VHDL-FPGA-Verilog] LMS_ DL : 0: Implement LMS vhdl code.
Date : 2026-01-10 Size : 1kb User : Hem
[VHDL-FPGA-Verilog] lms DL : 0: verilog 关于LMS均衡器的一些很有用的外文资料需要的下免费-verilogverilogverilogverilogverilogverilogverilog
Date : 2026-01-10 Size : 5.44mb User : 不懂什么
[VHDL-FPGA-Verilog] LMS_filter DL : 0: verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
Date : 2026-01-10 Size : 342kb User : rayax
[VHDL-FPGA-Verilog] fir_lms DL : 0: 基于FIR滤波器的自适用滤波器的实现 vhDL语言-FIR LMS
Date : 2026-01-10 Size : 1kb User : hejianhua
[VHDL-FPGA-Verilog] HDLImplementationoftheVariableStepSize DL : 0: proposes a Verilog implementation of the Normalized Least Mean Square (NLMS) adaptive algorithm, having a variable step size. The envisaged application is the identification of an unknown system. First the convergence of derived LMS algorithms was analyzed in a Simulink application.
Date : 2026-01-10 Size : 218kb User : 陳柏宇
[VHDL-FPGA-Verilog] rs232 DL : 0: FPGA 数字滤波算法资料，自己可以设计等LMS 算法-FPGA Digital Filter Algorithm for information, they can design LMS algorithm
Date : 2026-01-10 Size : 58kb User : suupy
[VHDL-FPGA-Verilog] lms DL : 0: verilog编写的lms算法模块，简单易用-lms module using verilog.It s simple.
Date : 2026-01-10 Size : 1kb User : 邓小伟
[VHDL-FPGA-Verilog] fir6dlms DL : 0: lms算法，自适应滤波器中使用fir滤波器对信号的码间干扰进行均衡-lms
Date : 2026-01-10 Size : 1kb User : lvchangbo
[VHDL-FPGA-Verilog] ERROR_COUNTING_BLOCK DL : 0: vhdl code for error counting blk in lms algorithm
Date : 2026-01-10 Size : 5kb User : lekshmi
[VHDL-FPGA-Verilog] WEIGHT_UPDATE_BLOCK DL : 0: weight updateblock of lms algorithm
Date : 2026-01-10 Size : 5kb User : lekshmi
[VHDL-FPGA-Verilog] LMS-vhdl-coad- DL : 0: 基于quartus的LMS 自适应滤波器代码，适合初学者 -The LMS adaptive filter based on quartus code, suitable for beginners
Date : 2026-01-10 Size : 15kb User : jialiangquan

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