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[VHDL-FPGA-Verilog] pwmled DL : 0: 一个霹雳灯的Verilog源程序，用PWM原理实现，产生了LED灯的渐弱效果-a thunderbolt lights Verilog source files, using PWM principle realized, LED lights have a gradual effect of the weak
Date : 2026-01-09 Size : 499kb User : 张伟
[VHDL-FPGA-Verilog] xunhuandeng DL : 0: 在spartan－3e上利用八个led实现流水灯效果-Spartan-3e in the use of eight led lights to achieve the effect of flowing water
Date : 2026-01-09 Size : 5kb User : 唐江洲
[VHDL-FPGA-Verilog] liushuideng DL : 0: 流水灯程序，１．在ＣＨ－３实验平台上通过ＬＥＤ０～ＬＥＤ７八位ＬＥＤ发光二极管实现流水灯显示，流水效果为LED灯依次亮起，第二个灯亮时第一个熄灭２．用按键切换产生２种流水效果-Process water lights, 1. CH-3 in the experimental platform LED0 ~ LED7 through eight light-emitting diode LED lights show the achievement of water, running water followed by the effect of LED lights turn on, and the second when the lights go out the first 2. Key switch with two kinds of water have the effect of
Date : 2026-01-09 Size : 1.69mb User : 赵剑平
[VHDL-FPGA-Verilog] 8led DL : 0: verilog HDL上的8段LED跑马灯效果，Q2开发的希望对各位初学者有用-verilog HDL on the effect of 8-segment LED Marquee, Q2 development you want to be useful for beginners
Date : 2026-01-09 Size : 322kb User : zxf
[VHDL-FPGA-Verilog] PRJ DL : 0: 四个 LED 从左到右依次点亮（跑马灯效果），周而复始；按下复位按键后，四个 LED 熄灭，然后再恢复到跑马灯的效果。-4 LED light up from left to right (Marquee effect), again and again press the reset button, the four LED is off, then back to the Marquee effect.
Date : 2026-01-09 Size : 87kb User : qiutian
[VHDL-FPGA-Verilog] DF2C8_02_Key_SW_LED DL : 0: 1：按下复位按键，四个 LED 熄灭 2：如果拨码开关全部为 OFF 状态（输入 1111），四个 LED 从左到右依次点亮（跑马灯效果），周而复始； 3：如果拨码开关不全为 OFF 状态（输入 0000~1110），四个 LED从左到右依次点亮（跑马灯效果），周而复始； 4：如果按下四个轻触按键中的任意一个，LED 将全部点亮，放开按键后 LED 将恢复到左移或右移操作，但移位操作的计时器在按键按下时将继续计数。-1: Press the reset button, four LED off 2: If the DIP switch to OFF state of all the (input 1111), four LED lights from left to right (Marquee effect), again and again 3: If the DIP switch incomplete for the OFF state (enter 0000 ~ 1110), four LED lights from left to right (Marquee effect), again and again 4: If you press any of the four touch of a button, LED will be fully lit, After the release button LED will revert to the left or right operation, but the shift operation of the timer in the button press will continue to count.
Date : 2026-01-09 Size : 336kb User : qiutian
[VHDL-FPGA-Verilog] 6 DL : 0: 4位数码扫描显示电路,我们控制一个七段LED需要8个输出端口；如果要输出四位十进制数，就需要32的输出端口，这将占用大量的端口资源。采用串行扫描显示，我们只需要8+4共12个端口即可。其原理是：用一个四位的输出端控制，某一时刻只选中其中的一个LED（输出为‘1’表示选中），八位的输出端将该LED所需要显示的值输出；然后四位的输出端值改变，选中下一个LED。这样依次类推。如果选择的频率很快，达到50Hz以上，由于人眼的视觉暂留效应，看起来就像4个LED同时显示。设计一个程序，输入四个一位十进制数，用4个LED显示出来。CLK采用频率可调信号发生器，逐渐改变频率，观察扫描频率的改变对输出效果的影响。输入：连续脉冲，逻辑开关；输出：七段LED。 -4 digital scanning display circuit, we need to control a seven-segment LED output port 8 If you want to output four decimal numbers, you need the output port 32, which will take up a lot of ports. Serial scans showed, we need only 8 of 12 ports can be+4. The principle is: the output of four with a control, a time to select only one LED (output 1 is selected), 8 output of the LED by the need to show the value of the output then The output value of the four changes, select the next LED. This and so on. If you select the frequency rapidly, reaching more than 50Hz, as the human eye s persistence of vision effect, looks like a 4 LED display simultaneously. Design a program, enter a decimal number four, with four LED display. CLK signal generator with adjustable frequency, gradually changing the frequency of observed changes in scan frequency effect on the output. Input: Continuous pulse, logic switches output: seven-segment LED.
Date : 2026-01-09 Size : 4kb User : 李小勇
[VHDL-FPGA-Verilog] led DL : 0: FPGA实现流水灯效果的Verilog程序- FPGA realizes the class lantern floated down river effect Verilog procedure
Date : 2026-01-09 Size : 144kb User : yuguo
[VHDL-FPGA-Verilog] music_player DL : 0: FPGA实现音乐播放器，蜂鸣器播音，LED点阵屏同步滚动显示歌词，与音乐同步效果好，按键控制播放、暂停、停止、重播。-FPGA realization of music players, broadcasting buzzer, LED dot matrix display screen, synchronized scrolling lyrics and music synchronization effect, buttons control play, pause, stop, replay.
Date : 2026-01-09 Size : 2.32mb User : 顿河战神
[VHDL-FPGA-Verilog] hongwai-LCD DL : 0: 通过红外线来控制LED及单片机处理的效果，用来简单的红外学习-Through infrared to control LED and SCM processing effect, used a simple infrared learning
Date : 2026-01-09 Size : 46kb User : 尹冰
[VHDL-FPGA-Verilog] FFT DL : 0: 大功率LED，一般指大于0.65W，这一点不同公司内部也会有不同的标准，因为目前在大功率LED领域还没有形成大家一致认可的行业标准。光强与流明比小功率大，但同样散热也很大，现在大功率大多是单颗应用，加上有效散热面积很大的散热片，也出现了集成在一起的LED灯矩阵，但是散热效果不是很好。小功率一般是0.06W左右的。现在LED手电一般是用小功率用的，光散不散，取决于LED的发光角度，有大角度小角度之分，小角度不散，大角度才散。市面上的手电筒一般是用草帽头做的。效果很好。现在就担心有些厂家不重质量，拿的次品LED做电筒，用不了多久就有死灯。-Power LED, generally refers to greater than 0.65W, this house will have different standards, consistent with recognized industry standards in the field of high power LED not yet formed. Light intensity and lumen than the low-power, but the same heat is also a great, and now power most single applications, coupled with effective cooling area a lot of heat sink, also appeared in the integrated LED lamp matrix, but the cooling effect not very good. Low-power is about 0.06W. The LED flashlight is generally with a small power, and scattered light lingers, depending on the LED light angle, large angle and small-angle points, small-angle ghost, only scattered large angle. Flashlight on the market with hat head. Good results. Now worried that some manufacturers are not quality, take the defective LED as flashlight, and will not be long before there dead lights.
Date : 2026-01-09 Size : 684kb User : 张无极
[VHDL-FPGA-Verilog] led DL : 0: 点亮EP2C5Q208C8N的LED流水灯，并实现流水灯的效果-To light EP2C5Q208C8N the LED light water, and water light effect
Date : 2026-01-09 Size : 355kb User : yunyifeng
[VHDL-FPGA-Verilog] exp5 DL : 0: 本实验要求完成的任务是在时钟信号的作用下，通过输入八位的拨动开关输入不同的数据，改变分频比，使输出端口输出不同频率的时钟信号，达到数控分频的效果。在实验中时，用八个拨动开关做为数据的输入，当八个拨动开关置为一个二进制数时，在输出端口输出对应频率的时钟信号，用户可以用示波器观察输出频率的变化，也可以使输出端口接LED灯来观察频率的变化。在此实验中我们把输出接入LED灯。-This experiment required to complete the task is the role of the clock signal, the different data are input through the input eight toggle switch to change the frequency dividing ratio so that the output port of the clock signals of different frequencies, to achieve the effect of NC divider. In the experiment, as the data input, eight toggle switch eight toggle switch is set to a binary number corresponding to the frequency of the clock signal at the output port, the user can observe the change of the output frequency with the oscilloscope LED light to observe the change of the frequency can also be connected to the output port. In this experiment, we access the output of the LED lights.
Date : 2026-01-09 Size : 316kb User : 真三战魂
[VHDL-FPGA-Verilog] Pll_prj DL : 0: FPGA中PLL模块的测试代码，代码通过例化一个PLL将25MHz系统时钟倍频到50MHz，然后通过两个不同频率时钟控制两个LED灯闪烁，通过闪烁频率可用观察PLL倍频效果-The FPGA PLL module test code, the code by instantiating a PLL to 25MHz system clock frequency doubling to 50MHz, and then by two different frequency clock control two LED lights flicker, flicker frequency can be used to observe the PLL multiplier effect
Date : 2026-01-09 Size : 142kb User : wicoboy
[VHDL-FPGA-Verilog] Lamp-from-left-to-right DL : 0: 接在P0口的8个LED从左到右循环依次点亮，产生走马灯效果-Then were lit in P0 port 8 LED from left to right cycle, resulting in a revolving door effect
Date : 2026-01-09 Size : 34kb User : 李先森
[VHDL-FPGA-Verilog] LED DL : 0: 控制led发光的Verilog代码，实现流水灯的效果。-Control led light Verilog code, to achieve the effect of light water.
Date : 2026-01-09 Size : 3kb User : 武磊
[VHDL-FPGA-Verilog] 3-x-3-button-light-water DL : 0: 该程序控制开发板上led依次点亮，达到流水灯的效果-The program control development in turn led panel lights, to the effect of light water
Date : 2026-01-09 Size : 434kb User : 郭功勋
[VHDL-FPGA-Verilog] sp6ex4 DL : 0: 流水灯实例，8个LED循环点亮，实现流水灯效果-Example of water lights, 8 LED cycle lit, to achieve the effect of water lights
Date : 2026-01-09 Size : 182kb User : chi