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[VHDL-FPGA-Verilog] quartusii DL : 0: 推荐!!!!!学ASIC相当不错的教程!!!!还是可以看看的-recommended !!!!! school ASIC fairly good tutorial! ! ! ! Or can see!
Date : 2026-01-07 Size : 825kb User : 安安
[VHDL-FPGA-Verilog] vector_to_int DL : 0: 改程序用VHDL编写实现由8位二进制数转化成整数的功能-convert vector to int
Date : 2026-01-07 Size : 3kb User : wuxueqiang
[VHDL-FPGA-Verilog] vector_to_int DL : 0: 将STD_LOGIC_VECTOR转换为int型-Will be converted to int type STD_LOGIC_VECTOR
Date : 2026-01-07 Size : 108kb User : 龚成
[VHDL-FPGA-Verilog] int DL : 0: PIC32MX4系列单片机中断模块示例代码 PIC32MX4系列单片机中断模块示例代码 PIC32MX4系列单片机中断模块示例代码-PIC32MX4 int PIC32MX4 int PIC32MX4 int PIC32MX4 int PIC32MX4 int
Date : 2026-01-07 Size : 16kb User : ludawei
[VHDL-FPGA-Verilog] int DL : 0: 通过按键中断来进行电平中断实验，本程序可以使用DEBUG模式进行在线调试-To carry out the experiment through the key level interrupt interrupted, the program can use DEBUG mode for online debugging
Date : 2026-01-07 Size : 10.6mb User : 赵莉
[VHDL-FPGA-Verilog] alpha1_3_compensator DL : 0: 同為適用於1.8V轉1.3V必迴路在1Mhz頻率下 RLC各為 25m 4.7u 10u 排除浮點數的int整數補償器給有需要的同學作為參考-The same applies to 1.8V 1.3V will turn 1Mhz frequency RLC circuit at each 25m 4.7u 10u exclude floating point int integer compensation to needy students as a reference
Date : 2026-01-07 Size : 1kb User : 王宇揚
[VHDL-FPGA-Verilog] Lab7 DL : 0: Adder Substrator 能夠顯示在FPGA上並且能夠實際作加減可做signed int -Adder Substrator
Date : 2026-01-07 Size : 14kb User : 夏宇婕
[VHDL-FPGA-Verilog] NIOS_Basic DL : 0: NIOS相关的基础实验的代码，SYSCLK,TIMESTAMP,LED,SDRAM,INT-NIOS basic experiments related to code, SYSCLK, TIMESTAMP, LED, SDRAM, INT
Date : 2026-01-07 Size : 2kb User : 李纪楷
[VHDL-FPGA-Verilog] Fast_SQRT DL : 0: 只使用简单的移位操作对32bit整型数进行开方的算法的Verilog实现-realize the sqrt algorithm which only use shift operation on 32bit int by Verilog
Date : 2026-01-07 Size : 4.97mb User : WangYibin
[VHDL-FPGA-Verilog] INT DL : 0: 基于FPGA的nios ii嵌入式中断应用开发程序，仅供参考学习使用，谢谢。-NIOS based on the II FPGA embedded interrupt application development process, only for reference learning to use, thank you.
Date : 2026-01-07 Size : 26.34mb User : 宁静
[VHDL-FPGA-Verilog] float_2_int.v DL : 0: 最全的，最简单，32位浮点数转整数，32位整数转浮点数，直接可以移植，已经测试过好用。(The most complete, the simplest, 32 bit floating-point integer, 32 integer floating point number, can be directly transplanted, has been tested, easy to use.)
Date : 2026-01-07 Size : 1kb User : 那里的星空
[VHDL-FPGA-Verilog] ACCx42_AvalonST_Input DL : 0: This module does pipelined accumulate operation with 42 bit int value, usually used in dsp, Proved in Altera Stratix FPGA devices
Date : 2026-01-07 Size : 2kb User : serg_86