Search - Histogram Equalization

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[VHDL-FPGA-Verilog] histogram4 DL : 0: 利用matlab和modelsim完成了用直方图均衡化处理灰色图片的前仿真，有处理前后图片的对比，verilog语言编写，但到用实时处理还差很远-Completed using matlab and modelsim deal with the gray image histogram equalization before the simulation, a comparison of before and after pictures, verilog language, but with real-time processing is very much far
Date : 2026-01-21 Size : 19.01mb User : 杨兔艳
[VHDL-FPGA-Verilog] histogram-equalization-verilog DL : 0: 直方图均衡的Verilog实现从Matlab读出图像为image.txt文件，经过Modelsim读入TXT文件进行直方图均衡处理，将输出结果再读出为image_he.txt文件，然后在Matlab观察直方图均衡增强效果。-The histogram equalization Verilog read from Matlab the image image.txt file after the Modelsim read into the TXT file, histogram equalization processing, and output the results read out for image_he.txt file, then the histogram equalization enhancement observed in Matlab.
Date : 2026-01-21 Size : 2kb User : 杨光