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[VHDL-FPGA-Verilog] ucGUI_3.24_NiosII_JimYang DL : 0: 嵌入式图形界面开发(NIOSII),uc/GUI 3.24 porting for NiosII 5.1 (SED1335 Controller)-Embedded GUI development (NIOSII), uc/GUI 3.24 porting for NiosII 5.1 (SED1335 Controller)
Date : 2025-12-22 Size : 463kb User : 老苏
[VHDL-FPGA-Verilog] Synopsys_Graphical_Environment_User_Guide DL : 0: Synopsis软件图形界面操作指南，对FPGA/ASIC初学者很有用！-Synopsis software GUI operation guide for the FPGA/ASIC is useful for beginners!
Date : 2025-12-22 Size : 1mb User : HY
[VHDL-FPGA-Verilog] XUPV2P_Base_System_Builder DL : 0: The Base System Builder (BSB) wizard is a software tool that help users quickly build a working system targeted at a specific development board. Based on the user’ s board selection, BSB will offer the user a number of options for creating a basic system on that board. These options include processor type, debug interface, cache configuration, memory type and size, and peripheral selection. For each option, functional default values will be preselected in the GUI.
Date : 2025-12-22 Size : 1.48mb User : marcus choi
[VHDL-FPGA-Verilog] 0987654 DL : 0: mini gui 应用于嵌入式视频程序开发设置，可以在ARM或MATLAB,FPGA中实现使用-mini gui application development for embedded video settings, you can ARM or MATLAB, FPGA implementation uses the
Date : 2025-12-22 Size : 1.77mb User : 武广录
[VHDL-FPGA-Verilog] LTM_User_Manual DL : 0: 友晶公司的LTM触摸屏开发必备资料，记录了里面的分辨率设置，配合这款硬件设备，对于研究uc/gui在nios中的移植有莫大的帮助。-Terasic of the LTM development of the necessary information on the touch screen to record the inside of the resolution setting, with this hardware device, for research uc/gui in nios in the transplant of great help.
Date : 2025-12-22 Size : 5.44mb User : 刘大明
[VHDL-FPGA-Verilog] encoder DL : 0: GUI to encode a video from an Axis Gige camera using mencoder. Mencoder needs to be installed before using this software. Parameters that can be modified are rame rate, resolution, inclusion of error resilience tools-GUI to encode a video from an Axis Gige camera using mencoder. Mencoder needs to be installed before using this software. Parameters that can be modified are rame rate, resolution, inclusion of error resilience tools...
Date : 2025-12-22 Size : 6kb User : Ashhly
[VHDL-FPGA-Verilog] NIOSII_logic DL : 0: 我曾经参加过电子设计，所以传一些以前的作品，大家看一下。这是一个居于NIOS和FPGA的嵌入式逻辑分析仪中nios的所有程序，里面包含彩屏程序，sd卡读取程序，以及gui式的设计界面，这大大节省了资源，克服了传统单片机和FPGA的通信的问题。大家可以借鉴一下，个人感觉用嵌入式来设计会方便多了。-longic base on nios and fpga ,ucgui
Date : 2025-12-22 Size : 1.66mb User : 林铭团
[VHDL-FPGA-Verilog] gui DL : 0: tft 4.3寸屏驱动代码在本机上测试通过-TFT 4.3 inch screen driver code in this machine through test
Date : 2025-12-22 Size : 4kb User : zhanghai
[VHDL-FPGA-Verilog] 24_lcd_gui DL : 0: fpga源码，供初学者使用，GUI系统说明-fpga source code, for beginners, GUI System Description
Date : 2025-12-22 Size : 5.41mb User : 李清政
[VHDL-FPGA-Verilog] PCIe_CIVGX_AVST_On_Chip_Mem DL : 0: Altera公司的pcie核，附有调试用的驱动和上位机-pcie hard ip of altera, with driver and debug GUI
Date : 2025-12-22 Size : 13.39mb User : 樵简
[VHDL-FPGA-Verilog] 24_lcd_gui DL : 0: 这个是我从黑金社区上找过来的是关于LDC/GUI系统设计的代码希望对大家学习FPGA有用-This is I can come the black community is on the LDC/GUI system design code, we hope to learn useful FPGA
Date : 2025-12-22 Size : 5.46mb User : Gent Liu
[VHDL-FPGA-Verilog] isjtc DL : 0: Use serial programming examples matlab GUI implementation, Independent component analysis for image processing, Realize image watermarking, de-noising, plus noise and other functions.
Date : 2025-12-22 Size : 4kb User : fyqdwg
[VHDL-FPGA-Verilog] 5540 DL : 0: Is a practical method of path planning, Normalized data model, modal vibration, Based on matlab GUI interface design.
Date : 2025-12-22 Size : 5kb User : lanjenliekie
[VHDL-FPGA-Verilog] xjrsb DL : 0: Based on matlab GUI interface design, Complete class-based image processing, contains all of the source code, auto image, Related impulse response analysis algorithm and inspection.
Date : 2025-12-22 Size : 12kb User : jienenfui
[VHDL-FPGA-Verilog] dg137 DL : 0: Based on matlab GUI interface design, It contains CV, CA, Single, current, constant turn rate, turning model, Simulation of the effect is very good.
Date : 2025-12-22 Size : 147kb User : 尤艳康
[VHDL-FPGA-Verilog] 8. FILTER DL : 0: DIGITAL FILTER GUI matlab
Date : 2025-12-22 Size : 875kb User : elkassas