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[VHDL-FPGA-Verilog] Fir Filter DL : 0: 2 D FIR Filter
Date : 2010-12-28 Size : 5.73kb User : sisi12343@sina.com
[VHDL-FPGA-Verilog] fir.tar DL : 0: FIR滤波器的VHDL语言实现-The implement of FIR Filter based on VHDL
Date : 2025-12-22 Size : 4kb User : 王晓东
[VHDL-FPGA-Verilog] FIR低通滤波器部分模块 DL : 0: 一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
Date : 2025-12-22 Size : 5kb User : 吴健宇
[VHDL-FPGA-Verilog] fir-vhdl DL : 0: 用Vhdl硬件描述语言编写的FIR数字滤波器-Vhdl using Hardware Description Languages in preparing the FIR digital filter
Date : 2025-12-22 Size : 5kb User : MAX
[VHDL-FPGA-Verilog] Fir DL : 0: 11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated
Date : 2025-12-22 Size : 1kb User : shenyunfei
[VHDL-FPGA-Verilog] fir DL : 0: 完成一个FIR数字滤波器的设计。要求： 1、基于直接型和分布式两种算法。 2、输入数据宽度为8位，输出数据宽度为16位。 3、滤波器的阶数为16阶，抽头系数分别为h[0]=h[15]=0000，h[1]=h[14]=0065，h[2]=h[13]=018F，h[3]=h[12]=035A，h[4]=h[11]=0579，h[5]=h[10]=078E，h[6]=h[9]=0935，h[7]=h[8]=0A1F。 -Completion of a FIR digital filter design. Requirements: one, based on the direct type and distributed two algorithms. 2, input data width of 8, the output data width of 16. 3, filter order of 16 bands, tap coefficients for h [0] = h [15] = 0000, h [1] = h [14] = 0065, h [2] = h [13] = 018F , h [3] = h [12] = 035A, h [4] = h [11] = 0579, h [5] = h [10] = 078E, h [6] = h [9] = 0935, h [7] = h [8] = 0A1F.
Date : 2025-12-22 Size : 5kb User : fredyu
[VHDL-FPGA-Verilog] fir DL : 0: FIR数字滤波器程序，采用vhdl编写，可用于FPGA电路-FIR digital filter procedure for the preparation of VHDL can be used in FPGA circuit
Date : 2025-12-22 Size : 169kb User : zhao onely
[VHDL-FPGA-Verilog] FIR DL : 0: 此文件包括FIR滤波器的设计对EDA的介绍，以及用VHDL语言实现FIR滤波器的FPGA实现-This document includes the design of FIR filters on the EDA
Date : 2025-12-22 Size : 2.41mb User : solor1985
[VHDL-FPGA-Verilog] fir DL : 0: Verilog 程序，实现4阶 fir-filter滤波器。 -Verilog procedures, to achieve 4-order filter fir-filter.
Date : 2025-12-22 Size : 1kb User : 左麟
[VHDL-FPGA-Verilog] ver-fir-coefficient DL : 0: vhdl source,ver-fir-coefficient,simulink of fir with soft ware input
Date : 2025-12-22 Size : 390kb User : heti
[VHDL-FPGA-Verilog] fir DL : 1: 我自己用VHDL语言编的16阶FIR数字滤波器，仿真是在Quartus II上通过的，对大家一定有帮助的，压缩文件里还有详细的设计说明呢，肯定让你完全了解数字滤波器的设计。-VHDL language with my own series of 16-order FIR digital filter in the Quartus II simulation is adopted, the U.S. will certainly be helpful, compressed document also detailed design description, it certainly allows you to fully understand the digital filter设计.
Date : 2025-12-22 Size : 888kb User : 王志
[VHDL-FPGA-Verilog] FIR DL : 0: ＦＰＧＡ实现数字滤波器，基于硬件描述语言ＶＥＲＩＬＯＧ　ＨＤＬ，顶层文件ＦＩＲ．Ｖ-FPGA realization of digital filters, based on the hardware description language VERILOG HDL, the top-level file FIR. V
Date : 2025-12-22 Size : 5kb User : YP
[VHDL-FPGA-Verilog] FIR DL : 0: FIR数字滤波器分布式算法的原理及FPGA实现-Distributed Arithmetic FIR digital filter FPGA Principle and realize
Date : 2025-12-22 Size : 585kb User : 王杰
[VHDL-FPGA-Verilog] FIR DL : 0: 用verilog设计的FIR滤波器。滤波器需要很快的处理速度，所以采用了wallace树算法，超前进位加法器-The FIR filter is designed with verilog. To improve the process speed, wallace tree and fast-carrylook-aheadarithmetic were used.
Date : 2025-12-22 Size : 317kb User : simeon chan
[VHDL-FPGA-Verilog] FIR DL : 1: 基于FPGA的FIR滤波器设计思想，里面有很好的算法供大家参考-FPGA-based FIR filter design ideas, there are very good for your reference algorithm
Date : 2025-12-22 Size : 614kb User : 菠萝
[VHDL-FPGA-Verilog] FIR DL : 0: FIR在FPGA中的VHDL代码实现教程-FIR in FPGA code in VHDL Tutorial
Date : 2025-12-22 Size : 20kb User : Mr Yang
[VHDL-FPGA-Verilog] fir DL : 0: 利用FPGA中verlog HDL实现FIR滤波功能,可自行设置相关参数，生成模块-Verlog HDL in the use of FPGA realization of FIR filtering, the provision of the relevant parameters can generate module
Date : 2025-12-22 Size : 887kb User : libaogang
[VHDL-FPGA-Verilog] fir-vhdl-code DL : 0: FIR FILTER CODE with VHDL
Date : 2025-12-22 Size : 112kb User : mahmoud
[VHDL-FPGA-Verilog] verilog.DA.FIR.. DL : 1: 用verilog写的16阶串行DA算法FIR滤波器-Verilog written by 16-order FIR filter serial DA algorithm
Date : 2025-12-22 Size : 563kb User : 代鑫
[VHDL-FPGA-Verilog] fir DL : 0: code for fir filter see it is from altera site.-code for fir filter see it is from altera site.
Date : 2025-12-22 Size : 26kb User : bris

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