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[VHDL-FPGA-Verilog] DDS小数分频 DL : 0: 文件列表(点击判断是否您需要的文件，如果是垃圾请在下面评价投诉): DDS小数分频 ...........\Block1.vhd.bak ...........\db ...........\..\add_sub_9mh.tdf ...........\..\DDS.asm.qmsg ...........\..\DDS.asm_labs.ddb ...........\..\DDS.cbx.xml ...........\..\DDS.cmp.bpm ...........\..\DDS.cmp.cdb ...........\..\DDS.cmp.ecobp ...........\..\DDS.cmp.hdb ...........\..\DDS.cmp.logdb ...........\..\DDS.cmp.rdb ...........\..\DDS.cmp.tdb ...........\..\DDS.cmp0.ddb ...........\..\DDS.cmp2.ddb ...........\..\DDS.cmp_bb.cdb ...........\..\DDS.cmp_bb.hdb ...........\..\DDS.cmp_bb.logdb ...........\..\DDS.cmp_bb.rcf ...........\..\DDS.dbp ...........\..\DDS.db_info ...........\..\DDS.eco.cdb ...........\..\DDS.eds_overflow ...........\..\DDS.fit.qmsg ...........\..\DDS.fnsim.cdb ...........\..\DDS.fnsim.hdb ...........\..\DDS.fnsim.qmsg ...........\..\DDS.hier_info ...........\..\DDS.hif ...........\..\DDS.map.bpm ...........\..\DDS.map.cdb ...........\..\DDS.map.ecobp ...........\..\DDS.map.hdb ...........\..\DDS.map.logdb ...........\..\DDS.map.qmsg ...........\..\DDS.map_bb.cdb ...........\..\DDS.map_bb.hdb ...........\..\DDS.map_bb.logdb ...........\..\DDS.pre_map.cdb ...........\..\DDS.pre_map.hdb ...........\..\DDS.psp ...........\..\DDS.pss ...........\..\DDS.rtlv.hdb ...........\..\DDS.rtlv_sg.cdb ...........\..\DDS.rtlv_sg_swap.cdb ...........\..\DDS.sgdiff.cdb ...........\..\DDS.sgdiff.hdb ...........\..\DDS.signalprobe.cdb ...........\..\DDS.sim.cvwf ...........\..\DDS.sim.hdb ...........\..\DDS.sim.qmsg ...........\..\DDS.sim.rdb ...........\..\DDS.sld_design_entry.sci ...........\..\DDS.sld_design_entry_dsc.sci ...........\..\DDS.syn_hier_info ...........\..\DDS.tan.qmsg ...........\..\prev_cmp_DDS.asm.qmsg ...........\..\prev_cmp_DDS.fit.qmsg ...........\..\prev_cmp_DDS.map.qmsg ...........\..\prev_cmp_DDS.sim.qmsg ...........\..\prev_cmp_DDS.tan.qmsg ...........\..\wed.wsf ...........\DDS.asm.rpt ...........\DDS.bdf ...........\DDS.done ...........\DDS.dpf ...........\DDS.fit.rpt ...........\DDS.fit.smsg ...........\DDS.fit.summary ...........\DDS.flow.rpt ...........\DDS.map.rpt ...........\DDS.map.summary ...........\DDS.pin ...........\DDS.pof ...........\DDS.qpf ...........\DDS.qsf ...........\DDS.sim.rpt ...........\DDS.sof ...........\DDS.tan.rpt ...........\DDS.tan.summary ...........\DDS.vhd ...........\DDS.vhd.bak ...........\DDS.vwf ...........\lpm_add_sub0.bsf ...........\lpm_add_sub0.inc ...........\lpm_add_sub0.tdf ...........\lpm_add_sub0_waveforms.html ...........\lpm_add_sub1.bsf ...........\lpm_add_sub1.inc ...........\lpm_add_sub1.tdf ...........\lpm_add_sub1_waveforms.html ...........\lpm_add_sub2.bsf ...........\lpm_add_sub2.inc ...........\lpm_add_sub2.tdf ...........\lpm_add_sub2_waveforms.html ...........\parallel_add0.bsf
Date : 2009-05-03 Size : 495.98kb User : beijbinghe@163.com
[VHDL-FPGA-Verilog] dds正弦发生器代码 DL : 0: 讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output
Date : 2025-12-29 Size : 480kb User : czy
[VHDL-FPGA-Verilog] dds-design DL : 0: * DESCRIPTION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DESCRIPTION : DDS BY PLD design Online.** AUTHOR : Sun Yu** HISTORY : 12/06/2002*
Date : 2025-12-29 Size : 1kb User : 魏杰
[VHDL-FPGA-Verilog] dds-design DL : 0: DDS design with vhdl language.
Date : 2025-12-29 Size : 1kb User :
[VHDL-FPGA-Verilog] dds DL : 0: 用FPGA实现DDS,可变频,幅值由硬件完成-Using FPGA realize DDS, can be frequency, amplitude from hardware to complete
Date : 2025-12-29 Size : 659kb User : liuyu
[VHDL-FPGA-Verilog] DDS-2 DL : 0: 用FPGA实现DDS的原理图，结构清晰，采用总线方式与外部单片机通信-FPGA realization of DDS with the schematic diagram, structural clarity, the use of bus-way communication with the outside Singlechip
Date : 2025-12-29 Size : 13kb User : 赵培立
[VHDL-FPGA-Verilog] DDS DL : 0: 用51和 FPGA实现的 DDS的程序-FPGA with 51 and realize the process of DDS
Date : 2025-12-29 Size : 5kb User : 胡玉贵
[VHDL-FPGA-Verilog] dds DL : 0: 基于飓风1 fpga 和stc单片机的dds信号源程序是自己些的能用最大频率是2M-1 fpga based on the hurricane and STC dds SCM signal source more of their own can use the maximum frequency is 2M
Date : 2025-12-29 Size : 354kb User : 阿斯顿
[VHDL-FPGA-Verilog] dds DL : 0: 基于CYCLONE II的程序,DDS原理的函数信号发生器.采用查表法实现.各位可以参考.-CYCLONE II based on the procedure, DDS Function Generator principle. Realize the use of look-up table method. Members may refer to.
Date : 2025-12-29 Size : 226kb User : Yin
[VHDL-FPGA-Verilog] dds DL : 0: DDS正弦信号发生器频率和相位连续可调。频率最大2M
Date : 2025-12-29 Size : 3kb User : dsf
[VHDL-FPGA-Verilog] dds DL : 0: DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
Date : 2025-12-29 Size : 1.31mb User : 谭儆轩
[VHDL-FPGA-Verilog] dds DL : 0: 利用fpga实现的DDS，可输出正弦波，输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable
Date : 2025-12-29 Size : 458kb User : qlg
[VHDL-FPGA-Verilog] dds DL : 0: 实现dds功能，利用quartus软件，子模块包括加法器，锁相环，date-rom 利用原图将各模块综合，利用ps2键盘控制频率及相位。-Dds realize functions, using Quartus software, sub-modules including the adder, phase-locked loop, date-rom image to the module using integrated, using ps2 keyboard to control the frequency and phase.
Date : 2025-12-29 Size : 2.72mb User : lijingfeng
[VHDL-FPGA-Verilog] vhdl-dds DL : 0: fpga 控制dds 程序。希望对各位有用-dds FPGA control procedures. Members wish to be useful
Date : 2025-12-29 Size : 86kb User : martin
[VHDL-FPGA-Verilog] DDS DL : 0: DDS调试心得,VERIOLG 各HDL和VHDL语言的DDS调试方法-DDS debugging experience, VERIOLG the HDL and VHDL languages DDS debugging method
Date : 2025-12-29 Size : 52kb User : 李达兴
[VHDL-FPGA-Verilog] DDS DL : 0: DDS的频率转换可以以近似认为是即时的，这是因为它的相位序列在时间上是离散的，在频率控制字改变之后，要经过一个时钟周期之后才能按照新的相位增量增加，所以也可以说它的频率转换时间就是频率控制字的传输时间，-DDS frequency conversion can be considered similar to real-time, this is because it is the phase sequence in time is discrete, in the frequency control word change after one clock cycle to go through before a new phase in accordance with the incremental increase, so it can be said of the frequency switching time is the frequency control word transmission time,
Date : 2025-12-29 Size : 2mb User : lqb
[VHDL-FPGA-Verilog] dds DL : 0: 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
Date : 2025-12-29 Size : 547kb User : 陈阳
[VHDL-FPGA-Verilog] DDS DL : 0: DDS原理介绍，里面是有时序图和系统设计！-DDS principle that there is a timing diagram and system design!
Date : 2025-12-29 Size : 444kb User : dragon
[VHDL-FPGA-Verilog] DDS DL : 0: 《DDS原理简介(中文)》DDS即直接数字频率合成器，原理及系统设计实现- DDS Principle Introduction (Chinese) DDS direct digital frequency synthesizer, the principle and system design to achieve
Date : 2025-12-29 Size : 444kb User : 范田田
[VHDL-FPGA-Verilog] dds DL : 0: dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
Date : 2025-12-29 Size : 1.04mb User : liulei

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