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[VHDL-FPGA-Verilog] two_d_dct_serial DL : 1: altera公司提供的适用于包涵DSP内核的FPGA的二维DCT变换源码，语言是：verilog 性能不错，不过资源消耗有点大，可以用来学习多项式变换的DCT算法-ALTERA companies covered in the application of FPGA DSP core 2D DCT source language is : Verilog performance is good, but a bit large consumption of resources can be used to transform learning polynomial algorithm DCT
Date : 2025-12-23 Size : 24kb User : 猪猪
[VHDL-FPGA-Verilog] ad_DCT DL : 0: verilog 编程有测试文档基于查表结构实现离散余弦变换dct 来源：opencores -Verilog Programming is based on the test documents Lookup structure for a discrete cosine transform Extra Source : opencores
Date : 2025-12-23 Size : 33kb User : 周信均
[VHDL-FPGA-Verilog] 20060412183015974 DL : 0: 是关于dct的Verilog HDL源代码和测试程序-on the Verilog HDL source code and testing procedures
Date : 2025-12-23 Size : 30kb User : 凌风
[VHDL-FPGA-Verilog] dct DL : 0: 里面含有vhdl和verilog 版本,很好用!dct变换用得很多啊!-Which contains a VHDL and Verilog versions of very good use! Dct transform with a lot ah!
Date : 2025-12-23 Size : 122kb User : 萧勇
[VHDL-FPGA-Verilog] DCT DL : 0: 用verilog语言实现DCT编解码附有DCT的说明-Using Verilog language realize DCT codec with a description of DCT
Date : 2025-12-23 Size : 64kb User : 周韧研
[VHDL-FPGA-Verilog] dct DL : 0: 离散余弦变换的verilog源代码，经过验证可实现-Discrete cosine transform of Verilog source code can be verified
Date : 2025-12-23 Size : 27kb User : 罗伟
[VHDL-FPGA-Verilog] Dct_verilog DL : 0: 采用verilog hdl 语言实现整形dct算法，设计合理，算法简单，是红色逻辑开发板试验程序，值得一看。-Verilog hdl language used plastic realize DCT algorithm, rational design algorithm is simple and logical development board is red test procedures, worth a visit.
Date : 2025-12-23 Size : 4kb User : panyouyu
[VHDL-FPGA-Verilog] DCT_1D DL : 0: 一维DCT变换的verilog源码，可用于JPEG算法优化的参考。程序中用到的算法称为“扭卷积”，可参考相关IEEE paper-One-dimensional DCT transform Verilog source code can be used to optimize the JPEG algorithm reference. Procedures used in the algorithm known as the
Date : 2025-12-23 Size : 53kb User : 楚天
[VHDL-FPGA-Verilog] erweiDCT DL : 0: 一种改进的一维DCT方案设计与实现,采用VHDL实现,DCT以及IDCT-A one-dimensional DCT to improve program design and implementation using VHDL realize, DCT and IDCT
Date : 2025-12-23 Size : 126kb User : 小金
[VHDL-FPGA-Verilog] dct DL : 0: 2维DCt源码，可以实现8乘8点数据的2维DCT变换 -2-D DCT-source, you can realize 8 x 8 data 2-D DCT transform
Date : 2025-12-23 Size : 5kb User : jz
[VHDL-FPGA-Verilog] DCT+ DL : 0: 改进的DCT算法设计，veriloghdl实现-Improved DCT algorithm design, veriloghdl realize
Date : 2025-12-23 Size : 306kb User : lyc84122
[VHDL-FPGA-Verilog] DCT DL : 0: altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim 验证，文件中包含TESTBENCH ，直接可用-altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available
Date : 2025-12-23 Size : 14.69mb User : alison
[VHDL-FPGA-Verilog] DCT DL : 0: 用于视频图像编码的8×8DCT变换，可用于MPEG4.H263等VHDL编程-For video images encoded 8 × 8DCT transform, can be used to MPEG4.H263 such as VHDL Programming
Date : 2025-12-23 Size : 106kb User : zs
[VHDL-FPGA-Verilog] dct-code DL : 0: 离散余弦变换的VHDL实现，不错的代码和方法-Discrete cosine transform VHDL realization of good code and methods
Date : 2025-12-23 Size : 30kb User : 宋雪兵
[VHDL-FPGA-Verilog] butterfly DL : 0: 蝶形运算，可用于DCT变换，FFT变换的模块-Butterfly computation, can be used for DCT transform, FFT transform module
Date : 2025-12-23 Size : 1kb User : 过时无双
[VHDL-FPGA-Verilog] jpeg.tar DL : 0: This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is not limited. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image. Its quality is comparable to software solutions.
Date : 2025-12-23 Size : 3.26mb User : Bill Guan
[VHDL-FPGA-Verilog] dct DL : 0: 用vhdl语言来实现了dct离散余弦变换-With VHDL language to achieve the optimal discrete cosine transform
Date : 2025-12-23 Size : 7kb User : yaxin324
[VHDL-FPGA-Verilog] dct DL : 0: all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b.
Date : 2025-12-23 Size : 1kb User : haziq36
[VHDL-FPGA-Verilog] DCT-Implementation DL : 0: The 8x8 discrete cosine transform (DCT) is an efficient, real-valued transform often used in image compression. Special, fast algorithms for the DCT have been developed to accommodate the many arithmetic operations involved in implementing the DCT directly.
Date : 2025-12-23 Size : 265kb User : zpy
[VHDL-FPGA-Verilog] verilog dct DL : 0: 其使用模块的代码风格来编写，能够8点dct的转换(Its use of the module's code style to write, to 8 dct conversion)
Date : 2025-12-23 Size : 34kb User : 未曾走远

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