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[VHDL-FPGA-Verilog] pinglvhecheng DL : 0: 程序用VHDL实现：频率合成，DDS 主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
Date : 2025-12-25 Size : 142kb User : 刘赛
[VHDL-FPGA-Verilog] VHDL_Examples_for_education DL : 0: VHDL代码编程,集合了众多优秀的实例,胜过任何一本书的例子,作为教学或程序开发中调用非常合适!-VHDL code programming, a combination of a large number of outstanding examples are better than any one book's examples, as a teaching program or call very appropriate!
Date : 2025-12-25 Size : 58kb User : 赵康
[VHDL-FPGA-Verilog] yyin DL : 0: 这是一个语音程序,通过VHDL编译了.大家可以直接调用.其中还包括了键盘程序有需要可以下来-This a voice procedures, through a VHDL compiler. you can directly call. It also includes a keyboard procedures need to look at it down
Date : 2025-12-25 Size : 166kb User : 李飞
[VHDL-FPGA-Verilog] clk_div2n DL : 0: 这是用VHDL 语言编写的参数可以直接设置的2n倍时钟分频器，在运用时，不需要阅读VHDL源代码，只需要把clk_div2n.vhd加入当前工程便可以直接调用clk_div2n.bsf。-This is the VHDL language parameters can be directly installed 2n times the clock dividers, when exercising not reading VHDL source code, clk_div2n.vhd simply need to present the project can directly call clk_div2n. bsf.
Date : 2025-12-25 Size : 1kb User : 谢光华
[VHDL-FPGA-Verilog] MAX_UFM DL : 0: Altera epm240 的ufm调用。-Altera epm240 the UFM call.
Date : 2025-12-25 Size : 221kb User : Potossas
[VHDL-FPGA-Verilog] m21 DL : 0: 2选一数字选择器要的慢慢的来看现在我都设计好了可以直接调用就可以-2 selected one digital selector slowly to the point of view now I have a good design can directly call can
Date : 2025-12-25 Size : 136kb User : fuyuanxin
[VHDL-FPGA-Verilog] Random_Number_generator DL : 0: 此代码用于产生系统设计仿真阶段需要的仿真数据，运行的结果是一系列随机数。编译后可生成数据产生模块，在其他工程中之间调用之作为数据输入即可，对vhdl涉及仿真有一定的帮助-This code is used for creating a system design simulation stage of simulation data, the results of running a series of random numbers. Compiler can generate data generated modules, in other works as a call between the data input to the VHDL simulation involves a certain degree of help
Date : 2025-12-25 Size : 35kb User : 王弋妹
[VHDL-FPGA-Verilog] library DL : 0: 介绍VHDL中库的调用，使对库的调用有深入的了解-VHDL introduction of library calls, so call for the Treasury have a deeper understanding of
Date : 2025-12-25 Size : 3kb User : chenwen
[VHDL-FPGA-Verilog] task_function DL : 0: 自己编写的一个verilog HDL小程序，实现基本的task调用function的功能，对初学者有用。在xilinx的ISE仿真调试通过-I have written a verilog HDL small procedures, to achieve the basic function of the task to call the function, useful for beginners. In Xilinx s ISE simulation debugging through
Date : 2025-12-25 Size : 230kb User : lg
[VHDL-FPGA-Verilog] UART DL : 0: VHDL实现UART通信,包括发送和接叫程序，使用方便-VHDL realize UART communications, including sending and then call the procedure, ease of use
Date : 2025-12-25 Size : 8kb User : fdf
[VHDL-FPGA-Verilog] altera_up_avalon_ps2 DL : 0: 花了半个月才改好的Atera DE1/DE2 ps2 IP 驱动核。放在FPGA工程目录下可以直接使用。本IP能够驱动PS/2键盘和鼠标。使用时只要调用HAL目录下的文件即可以直接使用！-Spent a good two weeks we have made some changes Atera DE1/DE2 ps2 IP-driven nuclear. On the FPGA project directory can be used directly. The IP to drive PS/2 keyboard and mouse. When used as long as the call HAL directory file that can be used directly!
Date : 2025-12-25 Size : 27kb User : 王乔
[VHDL-FPGA-Verilog] gate DL : 0: verilog中调用门级电路的实验程序，实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode
Date : 2025-12-25 Size : 166kb User : 洪磊
[VHDL-FPGA-Verilog] SIM DL : 0: MODELSIM的实验程序，在QUARTUSii中调用MODELSIM，实现仿真-ModelSim Experimental procedures QUARTUSii call MODELSIM, realize Simulation
Date : 2025-12-25 Size : 149kb User : 洪磊
[VHDL-FPGA-Verilog] an486_design_example DL : 0: VHDL实现SPI接口转I2c接口的源代码，可以直接调用-VHDL realize I2C interface SPI interface to the source code, you can directly call
Date : 2025-12-25 Size : 362kb User : zw
[VHDL-FPGA-Verilog] I2C_Controller DL : 0: I2C控制器的源代码，Verilog HDL语言编写，可以直接调用-I2C controller source code, Verilog HDL language, you can directly call
Date : 2025-12-25 Size : 2kb User : zw
[VHDL-FPGA-Verilog] alu_16 DL : 1: 三种16位整数运算器的ALU设计方法，调用库函数74181（4位ALU），组成串行16位运算器。(用74181的正逻辑) B．调用库函数74181和74182，组成提前进位16位运算器。(用74181的正逻辑) 注意：调74181库设计，加进位是“0”有效，减借位是“1”有效，所以最高位进位或借位标志寄存器要统一调整到高有效 C．用always @，case方式描述16位运算器。-Three 16-bit integer arithmetic logic unit of the ALU design methodology, called library function 74181 (4 ALU), composed of serial 16-bit arithmetic logic unit. (With 74,181 positive logic) B. Call library functions 74181 and 74182 to form the advance into the 16-bit arithmetic logic unit. (With 74,181 positive logic) Note: 74,181 Treasury tune the design, add bit is
Date : 2025-12-25 Size : 1kb User : yifang
[VHDL-FPGA-Verilog] multiply DL : 0: 由verilog编写的乘法器，通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。-Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.
Date : 2025-12-25 Size : 3kb User : 金夕
[VHDL-FPGA-Verilog] vcs_simulation_mannual(Edition2) DL : 0: VCS-verilog compiled simulator是synopsys公司的产品.其仿真速度相当快,而且支持多种调用方式.该文档是一个不错的使用指南.-VCS-verilog compiled simulator is the Synopsys company s products. Its simulation at a fairly rapid pace, and support multiple call mode. This document is a good guide.
Date : 2025-12-25 Size : 174kb User : morisun
[VHDL-FPGA-Verilog] call DL : 0: verilog实现电梯的召唤功能，在quantusII环境下运行，包含工程文件和其他子文件-verilog to achieve the elevator call functions in quantusII environment to run, including engineering documents, and other sub-documents
Date : 2025-12-25 Size : 172kb User : bailu
[VHDL-FPGA-Verilog] Call-by-Value DL : 0: Describe a syntax of "Call by value"
Date : 2025-12-25 Size : 6kb User : Hank

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